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hitachi 16-bit single-chip microcomputer h8s/2319, h8s/2318 series, h8s/2319 f-ztat, h8s/2318 f-ztat, h8s/2315 f-ztat h8s/2319 hd64f2319 h8s/2318 hd6432318, hd64f2318 h8s/2317 hd6432317 h8s/2316 hd6432316 h8s/2315 hd64f2315 h8s/2313 hd6432313 h8s/2312 hd6412312 h8s/2311 hd6432311 h8s/2310 hd6412310 reference manual ?individual product specifications ade-602-188a rev. 2.0 8/24/00 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products.
main revisions and additions in this edition page item revisions (see manual for details) all whole sections amendment due to the addition of the h8s/2319 f-ztat, h8s/2315 f-ztat, h8s/2316, and h8s/2313 to the product lineup. 5 1.1 overview table 1.1 overview the product lineup added. 6 1.2 block diagram figure 1.1 block diagram note 1 amended due to the addition of wdtovf (fwe, emle). 7 1.3 pin arrangement figure 1.2 pin arrangement note amended due to the addition of wdtovf (fwe, emle). 8 figure 1.3 pin arrangement note amended due to the addition of wdtovf (fwe, emle). 10 1.4 pin functions in each operating mode table 1.2 pin functions in each operating mode functions for pins 32 to 39, 41 to 48, and 50 to 52 (tfp-100b) in flash memory programmer mode amended. function for pin 60 (tfp-100b) amended 12 note 3 amended. 15 1.5 pin functions table 1.3 pin functions emle pin added. 19 note 4 added. 20 1.6 product lineup note 2 added. 32 2.5 memory map in each operating mode figure 2.1 h8s/2319 f-ztat memory map in each operating mode added. 33 to 36, 42 figures 2.2, 2.3, and 2.7 memory map in each operating mode note on reserved area added. 37 figure 2.4 h8s/2316 memory map in each operating mode added. 38 to 40 figure 2.5 h8s/2315 f-ztat memory map in each operating mode added. 41 figure 2.6 h8s/2313 memory map in each operating mode added. 2.6 h8s/2318 series operating modes (f-ztat version) deleted (see the hardware manual).
page item revisions (see manual for details) 51 3.3.3 interrupt exception vector table table 3.3 interrupt sources, vector addresses, and interrupt priorities names for sci interrupts rxi0 and rxi1 amended. 54 3.5 interrupt response times table 3.8 interrupt response times number of wait states until execution instruction ends amended. 73 4.2.5 bus control register l (bcrl) description of bit 5 h8s/2319, h8s/2316, h8s/2315, and h8s/2313 added 177 5.13 pin states table 5.23 i/o port states in each processing state lwrod and daoen added to legend. 200 5.14.11 port g figure 5.35(a) port g block diagram (pin pg0) amended. 225 6.11 rom amended due to the addition of the h8s/2319 f- ztat to the product lineup. 252 7.1.4 a/d conversion characteristics table 7.8 a/d conversion characteristics nonlinearity error, offset error, full-scale error, quantization error, and absolute accuracy amended. 254 to 262 7.2 electrical characteristics of mask rom version (h8s/2318, h8s/2317) in low-voltage operation added. 263 7.3 electrical characteristics of f-ztat version (h8s/2318) table 7.19 absolute maximum ratings conditions a and b added. note amended. 264 to 267 7.3.2 dc characteristics tables 7.20 (a) and (b) dc characteristics maximum value of input leakage current, typical and maximum values of current dissipation, typical and maximum values of analog power supply voltage, typical and maximum values of reference power supply voltage, and equation in note 4 amended. 7.3.3 ac characteristics table 7.25 timing of on-chip supporting modules wdt overflow output delay time deleted. 275 7.3.4 a/d conversion characteristics table 7.26 a/d conversion characteristics nonlinearity error, offset error, full-scale error, quantization error, and absolute accuracy amended.
page item revisions (see manual for details) 277 to 280 7.3.6 flash memory characteristics tables 7.28 (a) and (b) flash memory characteristics completely replaced. 281 to 298 7.4 electrical characteristics of f-ztat version (h8s/2315) added. 7.3.1 notes when converting the f-ztat application software to the mask-rom versions (in the 1st edition) deleted (see the hardware manual). 305 8.1 list of registers (address order) h'ffc8: flmcr1 h'ffc9: flmcr2 h'ffcb: ebr2 amended. 345 8.3 functions h'fed5: bcrl description of bit 5 amended. 351 h'ff37: dtvecr description of bit 7 amended. 402, 403 h'ffc8: flmcr1 amended. 404, 405 h'ffc9: flmcr2 amended. 406 h'ffcb: ebr2 amended.

organization of h8s/2319, h8s/2318 series reference manual the following manuals are available for h8s/2319, h8s/2318 series. table 1 manuals title document code h8s/2600 series, h8s/2000 series programming manual ade-602-083a h8s/2339 series, h8s/2338 series, h8s/2329 series, h8s/2328 series, h8s/2319 series, h8s/2318 series hardware manual ade-602-171a (in preparation) h8s/2319, h8s/2318 series, h8s/2319 f-ztat, h8s/2318 f-ztat, h8s/2315 f-ztat reference manual ade-602-188a the h8s/2600 series, h8s/2000 series programming manual gives a detailed description of the architecture and instruction set of the h8s/2000 cpu. the h8s/2339 series, h8s/2338 series, h8s/2329 series, h8s/2328 series, h8s/2319 series, h8s/2318 series hardware manual describes the operation of on-chip functions, and gives a detailed description of the related registers. the h8s/2319, h8s/2318 series, h8s/2319 f-ztat, h8s/2318 f-ztat, h8s/2315 f-ztat reference manual mainly covers information specific to h8s/2319, h8s/2318 series and h8s/2318 f-ztat products, including pin arrangement, i/o ports, mcu operating modes (address maps), interrupt vectors, bus control, and electrical characteristics, and also includes a brief description of all i/o registers for the convenience of the user. the contents of h8s/2339 series, h8s/2338 series, h8s/2329 series, h8s/2328 series, h8s/2319 series, h8s/2318 series hardware manual and the h8s/2319, h8s/2318 series, h8s/2319 f-ztat, h8s/2318 f-ztat, h8s/2315 f-ztat reference manual are summarized in table 2.
table 2 contents of hardware manual and reference manual no. item hardware manual reference manual 1 overview (including pin arrangement) 2 mcu operating modes (including address maps) 3 exception handling 4 interrupt controller 5 bus controller 6 dma controller (dmac) 7 data transfer controller (dtc) 8 16-bit timer pulse unit (tpu) 9 programmable pulse generator (ppg) 10 8-bit timers 11 watchdog timer 12 serial communication interface (sci) 13 smart card interface 14 a/d converter 15 d/a converter 16 ram 17 rom (flash memory) 18 clock pulse generator 19 power-down modes 20 i/o ports (including port block diagrams) 21 electrical characteristics 22 register reference chart (in address order, with function summary) 23 instruction set 24 package dimension diagrams : included : included (with detailed register descriptions) ? not included
the following chart shows where to find various kinds of information for different purposes. overview pin arrangement diagram block diagrams of function modules pin functions electrical characteristics for product evaluation information, or comparative specification information for current users of hitachi products 1.1 overview 1.3 pin arrangement section 6 peripheral block diagrams 1.5 pin functions section 7 electrical characteristics i/o port information interrupts and exception handling information on other modules pin functions for detailed information on functions section 5 i/o ports section 3 exception handling and interrupt controller h8s/2339 series, h8s/2338 series, h8s/2329 series, h8s/2328 series, h8s/2319 series, h8s/2318 series hardware manual 1.5 pin functions list detailed descriptions 1.4 pin functions in each operating mode section 2 mcu operating modes list to find a register from its address to find register information by function setting procedure and notes for use as design material section 8 registers 8.1 list of registers (address order) 8.2 list of registers (by module) h8s/2339 series, h8s/2338 series, h8s/2329 series, h8s/2328 series, h8s/2319 series, h8s/2318 series hardware manual list operation description and notes program examples h8s/2600 series, h8s/2000 series programming manual for product specifications for details of operation of modules for information on operating modes for information on registers for information on instructions
the h8s/2339 series, h8s/2338 series, h8s/2329 series, h8s/2328 series, h8s/2319 series, and h8s/2318 series have the on-chip modules shown below table 3 h8s/2339, h8s/2338, h8s/2329, h8s/2328, h8s/2319, and h8s/2318 series on-chip modules on-chip module h8s/2339 series, h8s/2338 series h8s/2329 series, h8s/2328 series h8s/2319 series, h8s/2318 series cpu bus controller (busc) dram controller dma controller (dmac) data transfer controller (dtc) 16-bit timer pulse unit (tpu) (6 channels) (6 channels) (6 channels) programable pulse generator (ppg) 8-bit timer (2 channels) (2 channels) (2 channels) watchdog timer serial communication interface (sci) (3 channels) (3 channels) (2 channels) a/d converter (12 channels) (8 channels) (8 channels) d/a converter (4 channels) (2 channels) (2 channels) interrupt controller (intc) memory * product code rom (kbytes) ram (kbytes) product code rom (kbytes) ram (kbytes) product code rom (kbytes) ram (kbytes) h8s/2339 384 32 h8s/2329 384 32 h8s/2319 512 8 h8s/2338 256 8 h8s/2328 256 8 h8s/2318 256 8 h8s/2337 128 8 h8s/2327 128 8 h8s/2317 128 8 h8s/2332 8 h8s/2324 32 h8s/2316 64 8 h8s/2323 32 8 h8s/2315 384 8 h8s/2322r 8 h8s/2313 64 2 h8s/2320 4 h8s/2312 8 h8s/2311 32 2 h8s/2310 2 : on-chip : not on-chip note: * see the reference manual of each series for details.
i contents section 1 overview ............................................................................................................ 1 1.1 overview ................................................................................................................... ......... 1 1.2 block diagram .............................................................................................................. ..... 6 1.3 pin arrangement ............................................................................................................ .... 7 1.4 pin functions in each operating mode ............................................................................. 9 1.5 pin functions.............................................................................................................. ........ 13 1.6 product lineup ............................................................................................................. ...... 20 1.7 package dimensions ......................................................................................................... .21 section 2 mcu operating modes ................................................................................. 23 2.1 overview ................................................................................................................... ......... 23 2.1.1 operating mode selection (h8s/2318 f-ztat and h8s/2315 f-ztat versions)....................................... 23 2.1.2 operating mode selection (mask rom, romless, and h8s/2319 f-ztat versions)................................. 24 2.1.3 register configuration .............................................................................................. 25 2.2 register descriptions ...................................................................................................... ... 26 2.2.1 mode control register (mdcr) .......................................................................... 26 2.2.2 system control register (syscr)....................................................................... 26 2.2.3 system control register 2 (syscr2) (f-ztat version only) .......................... 28 2.3 operating mode descriptions ............................................................................................ 28 2.3.1 modes 1 to 3.......................................................................................................... 28 2.3.2 mode 4 (expanded mode with on-chip rom disabled) .................................... 28 2.3.3 mode 5 (expanded mode with on-chip rom disabled) .................................... 29 2.3.4 mode 6 (expanded mode with on-chip rom enabled)..................................... 29 2.3.5 mode 7 (single-chip mode)................................................................................. 29 2.3.6 modes 8 and 9 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only) ..... 29 2.3.7 mode 10 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only)............... 30 2.3.8 mode 11 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only)............... 30 2.3.9 modes 12 and 13 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only). 30 2.3.10 mode 14 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only)............... 30 2.3.11 mode 15 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only)............... 30 2.4 pin functions in each operating mode ............................................................................. 31 2.5 memory map in each operating mode ............................................................................. 31 section 3 exception handling and interrupt controller ......................................... 43 3.1 overview ................................................................................................................... ......... 43 3.1.1 exception handling types and priority................................................................ 43 3.2 interrupt controller ....................................................................................................... ..... 44
ii 3.2.1 interrupt controller features................................................................................. 44 3.2.2 pin configuration .................................................................................................. 44 3.3 interrupt sources ........................................................................................................... ..... 45 3.3.1 external interrupts................................................................................................. 45 3.3.2 internal interrupts.................................................................................................. 46 3.3.3 interrupt exception vector table ......................................................................... 46 3.4 interrupt control modes and interrupt operation .............................................................. 52 3.5 interrupt response times................................................................................................... 54 3.6 dtc activation by interrupt .............................................................................................. 55 3.6.1 overview............................................................................................................... 55 3.6.2 block diagram ...................................................................................................... 55 3.6.3 operation............................................................................................................... 5 6 section 4 bus controller .................................................................................................. 61 4.1 overview ................................................................................................................... ......... 61 4.1.1 features ................................................................................................................. 61 4.1.2 block diagram ...................................................................................................... 62 4.1.3 pin configuration .................................................................................................. 63 4.1.4 register configuration .......................................................................................... 64 4.2 register descriptions ...................................................................................................... ... 65 4.2.1 bus width control register (abwcr) ............................................................... 65 4.2.2 access state control register (astcr) .............................................................. 66 4.2.3 wait control registers h and l (wcrh, wcrl) .............................................. 66 4.2.4 bus control register h (bcrh) .......................................................................... 71 4.2.5 bus control register l (bcrl) ........................................................................... 72 4.3 overview of bus control ................................................................................................... 7 4 4.3.1 area partitioning................................................................................................... 74 4.3.2 bus specifications................................................................................................. 75 4.3.3 memory interfaces ................................................................................................ 76 4.3.4 advanced mode .................................................................................................... 76 4.3.5 chip select signals ............................................................................................... 77 4.4 basic bus interface........................................................................................................ ..... 79 4.4.1 overview............................................................................................................... 79 4.4.2 wait control.......................................................................................................... 79 4.5 burst rom interface ........................................................................................................ .. 81 4.5.1 overview............................................................................................................... 81 4.5.2 basic timing......................................................................................................... 81 4.5.3 wait control.......................................................................................................... 83 4.6 idle cycle ................................................................................................................. .......... 84 4.6.1 operation............................................................................................................... 8 4 4.6.2 pin states in idle cycle ......................................................................................... 87 4.7 bus release ................................................................................................................ ........ 87 4.7.1 overview............................................................................................................... 87
iii 4.7.2 operation............................................................................................................... 8 7 4.7.3 pin states in external-bus-released state............................................................ 88 4.7.4 transition timing ................................................................................................. 89 4.7.5 usage note ............................................................................................................ 90 4.8 bus arbitration............................................................................................................ ....... 90 4.8.1 overview............................................................................................................... 90 4.8.2 operation............................................................................................................... 9 0 4.8.3 bus transfer timing ............................................................................................. 90 4.8.4 note on use of external bus release ................................................................... 91 4.9 bus controller operation in a reset .................................................................................. 91 section 5 i/o ports ............................................................................................................. 93 5.1 overview ................................................................................................................... ......... 93 5.2 port 1 ..................................................................................................................... ............. 98 5.2.1 overview............................................................................................................... 98 5.2.2 register configuration .......................................................................................... 99 5.2.3 pin functions......................................................................................................... 101 5.3 port 2 ..................................................................................................................... ............. 110 5.3.1 overview............................................................................................................... 11 0 5.3.2 register configuration .......................................................................................... 110 5.3.3 pin functions......................................................................................................... 112 5.4 port 3 ..................................................................................................................... ............. 120 5.4.1 overview............................................................................................................... 12 0 5.4.2 register configuration .......................................................................................... 120 5.4.3 pin functions......................................................................................................... 123 5.5 port 4 ..................................................................................................................... ............. 125 5.5.1 overview............................................................................................................... 12 5 5.5.2 register configuration .......................................................................................... 125 5.5.3 pin functions......................................................................................................... 126 5.6 port a ..................................................................................................................... ............ 126 5.6.1 overview............................................................................................................... 12 6 5.6.2 register configuration .......................................................................................... 127 5.6.3 pin functions......................................................................................................... 130 5.6.4 mos input pull-up function................................................................................ 131 5.7 port b ..................................................................................................................... ............ 132 5.7.1 overview............................................................................................................... 13 2 5.7.2 register configuration .......................................................................................... 133 5.7.3 pin functions......................................................................................................... 135 5.7.4 mos input pull-up function................................................................................ 137 5.8 port c ..................................................................................................................... ............ 138 5.8.1 overview............................................................................................................... 13 8 5.8.2 register configuration .......................................................................................... 139 5.8.3 pin functions......................................................................................................... 141
iv 5.8.4 mos input pull-up function................................................................................ 143 5.9 port d ..................................................................................................................... ............ 144 5.9.1 overview............................................................................................................... 14 4 5.9.2 register configuration .......................................................................................... 145 5.9.3 pin functions......................................................................................................... 147 5.9.4 mos input pull-up function................................................................................ 148 5.10 port e.................................................................................................................... .............. 150 5.10.1 overview............................................................................................................... 1 50 5.10.2 register configuration .......................................................................................... 151 5.10.3 pin functions......................................................................................................... 15 3 5.10.4 mos input pull-up function................................................................................ 154 5.11 port f .................................................................................................................... .............. 156 5.11.1 overview............................................................................................................... 1 56 5.11.2 register configuration .......................................................................................... 157 5.11.3 pin functions......................................................................................................... 16 2 5.12 port g .................................................................................................................... ............. 165 5.12.1 overview............................................................................................................... 1 65 5.12.2 register configuration .......................................................................................... 166 5.12.3 pin functions......................................................................................................... 17 0 5.13 pin states ................................................................................................................ ............ 172 5.13.1 port states in each mode ...................................................................................... 172 5.14 i/o port block diagrams................................................................................................... . 178 5.14.1 port 1.................................................................................................................. ... 178 5.14.2 port 2.................................................................................................................. ... 182 5.14.3 port 3.................................................................................................................. ... 183 5.14.4 port 4.................................................................................................................. ... 186 5.14.5 port a .................................................................................................................. .. 187 5.14.6 port b .................................................................................................................. .. 188 5.14.7 port c .................................................................................................................. .. 189 5.14.8 port d .................................................................................................................. .. 190 5.14.9 port e.................................................................................................................. ... 191 5.14.10 port f................................................................................................................. .... 192 5.14.11 port g ................................................................................................................. ... 200 section 6 supporting module block diagrams ......................................................... 205 6.1 interrupt controller ....................................................................................................... ..... 205 6.1.1 features ................................................................................................................. 205 6.1.2 block diagram ...................................................................................................... 205 6.1.3 pins..................................................................................................................... ... 206 6.2 data transfer controller .................................................................................................. .. 206 6.2.1 features ................................................................................................................. 206 6.2.2 block diagram ...................................................................................................... 207 6.3 16-bit timer pulse unit .................................................................................................... . 208
v 6.3.1 features ................................................................................................................. 208 6.3.2 block diagram ...................................................................................................... 209 6.3.3 pins..................................................................................................................... ... 210 6.4 8-bit timer................................................................................................................ ......... 211 6.4.1 features ................................................................................................................. 211 6.4.2 block diagram ...................................................................................................... 212 6.4.3 pins..................................................................................................................... ... 213 6.5 watchdog timer............................................................................................................. .... 214 6.5.1 features ................................................................................................................. 214 6.5.2 block diagram ...................................................................................................... 214 6.5.3 pins..................................................................................................................... ... 215 6.6 serial communication interface......................................................................................... 215 6.6.1 features ................................................................................................................. 215 6.6.2 block diagram ...................................................................................................... 216 6.6.3 pins..................................................................................................................... ... 217 6.7 smart card interface ....................................................................................................... ... 218 6.7.1 features ................................................................................................................. 218 6.7.2 block diagram ...................................................................................................... 218 6.7.3 pins..................................................................................................................... ... 219 6.8 a/d converter (8 analog input channel version) ............................................................ 219 6.8.1 features ................................................................................................................. 219 6.8.2 block diagram ...................................................................................................... 220 6.8.3 pins..................................................................................................................... ... 221 6.9 d/a converter .............................................................................................................. ...... 222 6.9.1 features ................................................................................................................. 222 6.9.2 block diagram ...................................................................................................... 222 6.9.3 pins..................................................................................................................... ... 223 6.10 ram....................................................................................................................... ............ 224 6.10.1 features ................................................................................................................ . 224 6.10.2 block diagram ...................................................................................................... 224 6.11 rom (h8s/2319)............................................................................................................ ... 225 6.11.1 features ................................................................................................................ . 225 6.11.2 block diagrams..................................................................................................... 225 6.12 rom....................................................................................................................... ............ 227 6.12.1 features ................................................................................................................ . 227 6.12.2 block diagrams..................................................................................................... 227 6.13 clock pulse generator ..................................................................................................... .. 229 6.13.1 features ................................................................................................................ . 229 6.13.2 block diagram ...................................................................................................... 229 section 7 electrical characteristics ............................................................................... 231 7.1 electrical characteristics of mask rom version (h8s/2318, h8s/2317, h8s/2316, h8s/2313, h8s/2311) and romless version (h8s/2312, h8s/2310) ............................. 231
vi 7.1.1 absolute maximum ratings ................................................................................. 231 7.1.2 dc characteristics ................................................................................................ 232 7.1.3 ac characteristics ................................................................................................ 234 7.1.4 a/d conversion characteristics ........................................................................... 252 7.1.5 d/a conversion characteristics ........................................................................... 253 7.2 electrical characteristics of mask rom version (h8s/2318, h8s/2317) in low-voltage operation ................................................................................................. 254 7.2.1 absolute maximum ratings ................................................................................. 254 7.2.2 dc characteristics ................................................................................................ 255 7.2.3 ac characteristics ................................................................................................ 257 7.2.4 a/d conversion characteristics ........................................................................... 262 7.2.5 d/a conversion characteristics ........................................................................... 262 7.3 electrical characteristics of f-ztat version (h8s/2318) ............................................... 263 7.3.1 absolute maximum ratings ................................................................................. 263 7.3.2 dc characteristics ................................................................................................ 264 7.3.3 ac characteristics ................................................................................................ 269 7.3.4 a/d conversion characteristics ........................................................................... 275 7.3.5 d/a conversion characteristics ........................................................................... 276 7.3.6 flash memory characteristics .............................................................................. 277 7.4 electrical characteristics of f-ztat version (h8s/2315) (under development)........... 281 7.4.1 absolute maximum ratings ................................................................................. 281 7.4.2 dc characteristics ................................................................................................ 282 7.4.3 ac characteristics ................................................................................................ 287 7.4.4 a/d conversion characteristics ........................................................................... 293 7.4.5 d/a conversion characteristics ........................................................................... 294 7.4.6 flash memory characteristics .............................................................................. 295 7.5 usage note ................................................................................................................. ........ 298 section 8 registers ............................................................................................................. 299 8.1 list of registers (address order) ...................................................................................... 299 8.2 list of registers (by module) ........................................................................................... 307 8.3 functions .................................................................................................................. .......... 315
1 section 1 overview 1.1 overview the h8s/2319 and h8s/2318 series are series of microcomputers (mcus: microcomputer units), built around the h8s/2000 cpu, employing hitachi's proprietary architecture, and equipped with peripheral functions on-chip. the h8s/2000 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, facilitating migration from the h8/300, h8/300l, or h8/300h series. on-chip peripheral functions required for system configuration include data transfer controller (dtc) bus master, rom and ram memory, a 16-bit timer pulse unit (tpu), 8-bit timer, watchdog timer (wdt), serial communication interface (sci), a/d converter, d/a converter, and i/o ports. single-power-supply flash memory (f-ztat*) and mask rom versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching is thus speeded up, and processing speed increased. the features of the h8s/2319 and h8s/2318 series are shown in table 1.1. note: * f-ztat is a trademark of hitachi, ltd.
2 table 1.1 overview item specification cpu ? general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? high-speed operation suitable for realtime control ? maximum clock rate: 25 mhz ? high-speed arithmetic operations 8/16/32-bit register-register add/subtract: 40 ns (at 25 mhz operation) 16 16-bit register-register multiply: 800 ns (at 25 mhz operation) 32 ?16-bit register-register divide: 800 ns (at 25 mhz operation) ? instruction set suitable for high-speed operation ? sixty-five basic instructions ? 8/16/32-bit data transfer, arithmetic, and logic instructions ? unsigned/signed multiply and divide instructions ? powerful bit-manipulation instructions ? cpu operating mode ? advanced mode: 16-mbyte address space bus controller ? address space divided into 8 areas, with bus specifications settable independently for each area ? chip select output possible for each area ? choice of 8-bit or 16-bit access space for each area ? 2-state or 3-state access space can be designated for each area ? number of program wait states can be set for each area ? burst rom directly connectable ? external bus release function data transfer controller (dtc) ? can be activated by internal interrupt or software ? multiple transfers or multiple types of transfer possible for one activation source ? transfer possible in repeat mode, block transfer mode, etc. ? request can be sent to cpu for interrupt that activated dtc
3 item specification 16-bit timer pulse unit (tpu) ? 6-channel 16-bit timer on-chip ? pulse i/o processing capability for up to 16 pins ? automatic 2-phase encoder count capability 8-bit timer, 2 channels ? 8-bit up-counter (external event count capability) ? two time constant registers ? two-channel connection possible watchdog timer ? watchdog timer or interval timer selectable serial communication interface (sci), 2 channels ? asynchronous mode or synchronous mode selectable ? multiprocessor communication function ? smart card interface function a/d converter ? resolution: 10 bits ? input: 8 channels ? 6.7 ? minimum conversion time (at 20 mhz operation) ? single or scan mode selectable ? sample-and-hold function ? a/d conversion can be activated by external trigger or timer trigger d/a converter ? resolution: 8 bits ? output: 2 channels i/o ports ? 71 input/output pins, 8 input-only pins memory ? flash memory and mask rom ? high-speed static ram product name rom ram h8s/2319 * 512 kbytes 8 kbytes h8s/2318 256 kbytes 8 kbytes h8s/2317 128 kbytes 8 kbytes h8s/2316 64 kbytes 8 kbytes h8s/2315 * 384 kbytes 8 kbytes h8s/2313 64 kbytes 2 kbytes h8s/2312 8 kbytes h8s/2311 32 kbytes 2 kbytes h8s/2310 2 kbytes note: * under development interrupt controller ? nine external interrupt pins (nmi, irq0 to irq7 ) ? 43 internal interrupt sources ? eight priority levels settable
4 item specification power-down state ? medium-speed mode ? sleep mode ? module stop mode ? software standby mode ? hardware standby mode ? variable clock division ratio operating modes ? eight mcu operating modes (h8s/2318 f-ztat, h8s/2315 f-ztat) cpu external data bus mode operating mode description on-chip rom initial value maximum value 0 1 2 3 4 advanced expanded mode with disabled 16 bits 16 bits 5 on-chip rom disabled 8 bits 16 bits 6 expanded mode with on-chip rom enabled enabled 8 bits 16 bits 7 single-chip mode 8 9 10 advanced boot mode enabled 8 bits 16 bits 11 12 13 14 advanced user program mode enabled 8 bits 16 bits 15
5 item specification operating modes ? four mcu operating modes (mask rom version and romless version h8s/2319 f-ztat) cpu external data bus mode operating mode description on-chip rom initial value maximum value 1 2 3 4 * advanced expanded mode with on- chip rom disabled disabled 16 bits 16 bits 5 * expanded mode with on- chip rom disabled disabled 8 bits 16 bits 6 expanded mode with on- chip rom enabled enabled 8 bits 16 bits 7 single-chip mode enabled note: * only modes 4 and 5 are provided in the romless version. clock pulse generator ? built-in duty correction circuit package ? 100-pin plastic tqfp (tfp-100b) ? 100-pin plastic qfp (fp-100a) product condition a condition b condition c * 1 lineup operating power supply voltage 2.7 to 3.6 v 3.0 to 3.6 v 2.4 to 3.6 v operating frequency 2 to 20 mhz 2 to 25 mhz 2 to 14 mhz model hd64f2319 * 3 * 2 hd64f2318 * 3 o hd6432318 o o o hd6432317 o o o hd6432316 o o * 2 hd64f2315 * 3 * 2 hd6432313 o o * 2 hd6412312 o o hd6432311 o o hd6412310 o o o: products in the current lineup notes: 1. t a = ?0? to 85? (wide-range specifications) is not available for condition c. 2. under development 3. in planning stage
6 1.2 block diagram pe7/ d7 pe6/ d6 pe5/ d5 pe4/ d4 pe3/ d3 pe2/ d2 pe1/ d1 pe0/ d0 internal data bus peripheral data bus peripheral address bus pd7/ d15 pd6/ d14 pd5/ d13 pd4/ d12 pd3/ d11 pd2/ d10 pd1/ d9 pd0/ d8 port d v cc v cc v cc v ss v ss v ss v ss v ss v ss port a pa3/ a19 pa2/ a18 pa1/ a17 pa0/ a16 pb7/ a15 pb6/ a14 pb5/ a13 pb4/ a12 pb3/ a11 pb2/ a10 pb1/ a9 pb0/ a8 pc7/ a7 pc6/ a6 pc5/ a5 pc4/ a4 pc3/ a3 pc2/ a2 pc1/ a1 pc0/ a0 port b port c port 3 p35/ sck1/ irq 5 irq 4 cs0 cs1 cs7 cs2 cs3 irq7 cs6 adtrg irq6 pf6/ as rd hwr lwr irq3 wait irq2 dreqo back irq1 cs5 breq irq0 cs4 stby res wdtovf wdtovf figure 1.1 block diagram
7 1.3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p12/tiocc0/tclka/a22 p13/tiocd0/tclkb/a23 p14/tioca1 p15/tiocb1/tclkc p16/tioca2 p17/tiocb2/tclkd v ss p30/txd0 p31/txd1 p32/rxd0 p33/rxd1 p34/sck0/ irq4 irq5 back irq1 cs5 wait irq2 breqo lwr irq3 hwr rd as v ss extal xtal v cc stby res wdtovf breq irq0 cs4 adtrg irq6 cs3 irq7 cs6 cs2 cs1 cs7 cs0 wdtovf figure 1.2 pin arrangement (tfp-100b: top view)
8 p10/tioca0/a20 p11/tiocb0/a21 p12/tiocc0/tclka/a22 p13/tiocd0/tclkb/a23 p14/tioca1 p15/tiocb1/tclkc p16/tioca2 p17/tiocb2/tclkd v ss p30/txd0 p31/txd1 p32/rxd0 p33/rxd1 p34/sck0/ irq4 irq5 breq irq0 cs4 back irq1 cs5 wait irq2 breqo lwr irq3 hwr rd as v ss extal xtal v cc stby res wdtovf adtrg irq6 cs3 irq7 cs6 cs2 cs1 cs7 cs0 wdtovf figure 1.3 pin arrangement (fp-100a: top view)
9 1.4 pin functions in each operating mode table 1.2 shows the pin functions in each of the operating modes. table 1.2 pin functions in each operating mode pin no. pin name tfp-100b fp-100a mode 4 mode 5 mode 6 * 1 mode 7 * 1 flash memory programmer mode * 2 1 3 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka nc 2 4 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb nc 3 5 p14/tioca1 p14/tioca1 p14/tioca1 p14/tioca1 nc 4 6 p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc nc 5 7 p16/tioca2 p16/tioca2 p16/tioca2 p16/tioca2 nc 6 8 p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd nc 79v ss v ss v ss v ss v ss 8 10 p30/txd0 p30/txd0 p30/txd0 p30/txd0 nc 9 11 p31/txd1 p31/txd1 p31/txd1 p31/txd1 nc 10 12 p32/rxd0 p32/rxd0 p32/rxd0 p32/rxd0 nc 11 13 p33/rxd1 p33/rxd1 p33/rxd1 p33/rxd1 nc 12 14 p34/sck0/ irq4 irq4 irq4 irq4 irq5 irq5 irq5 irq5
10 pin no. pin name tfp-100b fp-100a mode 4 mode 5 mode 6 * 1 mode 7 * 1 flash memory programmer mode * 2 26 28 d11 d11 d11 pd3 fo3 27 29 d12 d12 d12 pd4 fo4 28 30 d13 d13 d13 pd5 fo5 29 31 d14 d14 d14 pd6 fo6 30 32 d15 d15 d15 pd7 fo7 31 33 v ss v ss v ss v ss v ss 32 34 a0 a0 pc0/a0 pc0 a0 33 35 a1 a1 pc1/a1 pc1 a1 34 36 a2 a2 pc2/a2 pc2 a2 35 37 a3 a3 pc3/a3 pc3 a3 36 38 a4 a4 pc4/a4 pc4 a4 37 39 a5 a5 pc5/a5 pc5 a5 38 40 a6 a6 pc6/a6 pc6 a6 39 41 a7 a7 pc7/a7 pc7 a7 40 42 v cc v cc v cc v cc v cc 41 43 a8 a8 pb0/a8 pb0 a8 42 44 a9 a9 pb1/a9 pb1 a9 43 45 a10 a10 pb2/a10 pb2 a10 44 46 a11 a11 pb3/a11 pb3 a11 45 47 a12 a12 pb4/a12 pb4 a12 46 48 a13 a13 pb5/a13 pb5 a13 47 49 a14 a14 pb6/a14 pb6 a14 48 50 a15 a15 pb7/a15 pb7 a15 49 51 v ss v ss v ss v ss v ss 50 52 a16 a16 pa0/a16 pa0 a16 51 53 a17 a17 pa1/a17 pa1 a17 52 54 a18 a18 pa2/a18 pa2 a18 53 55 a19 a19 pa3/a19 pa3 nc 54 56 p20/tioca3 p20/tioca3 p20/tioca3 p20/tioca3 oe ce we wdtovf wdtovf wdtovf wdtovf
11 pin no. pin name tfp-100b fp-100a mode 4 mode 5 mode 6 * 1 mode 7 * 1 flash memory programmer mode * 2 61 63 md2 md2 md2 md2 v ss 62 64 res res res res res stby stby stby stby pf7/ pf7/ pf7/ nc 70 72 pf6/ as as as rd rd rd hwr hwr hwr lwr irq3 lwr irq3 lwr irq3 irq3 wait irq2 dreqo wait irq2 dreqo wait irq2 dreqo irq2 back irq1 cs5 back irq1 cs5 back irq1 cs5 irq1 breq irq0 cs4 breq irq0 cs4 breq irq0 cs4 irq0
12 pin no. pin name tfp-100b fp-100a mode 4 mode 5 mode 6 * 1 mode 7 * 1 flash memory programmer mode * 2 91 93 p26/tioca5/ tmo0 p26/tioca5/ tmo0 p26/tioca5/ tmo0 p26/tioca5/ tmo0 nc 92 94 p27/tiocb5/ tmo1 p27/tiocb5/ tmo1 p27/tiocb5/ tmo1 p27/tiocb5/ tmo1 nc 93 95 pg0/ irq6 adtrg irq6 adtrg irq6 adtrg irq6 adtrg cs3 irq7 cs6 cs3 irq7 cs6 cs3 irq7 cs6 irq7 cs2 cs2 cs2 cs1 cs7 cs1 cs7 cs1 cs7 cs0 cs0 cs0 wdtovf
13 1.5 pin functions table 1.3 pin functions pin no. type symbol tfp-100b fp-100a i/o name and function power v cc 40, 65, 98 42, 67, 100 input power supply: for connection to the power supply. all v cc pins should be connected to the system power supply. v ss 7, 18, 31, 49, 68, 88 9, 20, 33, 51, 70, 90 input ground: for connection to ground (0 v). all v ss pins should be connected to the system power supply (0 v). clock xtal 66 68 input connects to a crystal oscillator. see section 18, in the hardware manual, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. extal 67 69 input connects to a crystal oscillator. the extal pin can also input an external clock. see section 18, in the hardware manual, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. 69 71 output system clock: supplies the system clock to an external device.
14 pin no. type symbol tfp-100b fp-100a i/o name and function operating mode control md2 to md0 61, 58, 57 63, 60, 59 input mode pins: these pins set the operating mode. the relation between the settings of pins md2 to md0 and the operating mode is shown below. these pins should not be changed while the h8s/2318 series is operating. ? fwe md2 md1 md0 operating mode 0 000 1 10 1 1 0 0 mode 4 1 mode 5 1 0 mode 6 1 mode 7 1 000 1 1 0 mode 10 1 mode 11 100 1 1 0 mode 14 1 mode 15
15 pin no. type symbol tfp-100b fp-100a i/o name and function operating mode control md2 to md0 61, 58, 57 63, 60, 59 input ? md2 md1 md0 operating mode 000 1 10 1 1 0 0 mode 4 1 mode 5 1 0 mode 6 * 1 mode 7 * note: * not used on romless version. system control res stby breq breqo back
16 pin no. type symbol tfp-100b fp-100a i/o name and function interrupts nmi 63 65 input nonmaskable interrupt: requests a nonmaskable interrupt. when this pin is not used, it should be fixed high. irq7 irq0 cs7 cs0 as rd hwr lwr wait
17 pin no. type symbol tfp-100b fp-100a i/o name and function 16-bit timer- pulse unit (tpu) tclkd to tclka 6, 4, 2, 1 8, 6, 4, 3 input clock input d to a: these pins input an external clock. tioca0, tiocb0, tiocc0, tiocd0 99, 100, 1, 2 1 to 4 i/o input capture/ output compare match a0 to d0: the tgr0a to tgr0d input capture input or output compare output, or pwm output pins. tioca1, tiocb1 3, 4 5, 6 i/o input capture/ output compare match a1 and b1: the tgr1a and tgr1b input capture input or output compare output, or pwm output pins. tioca2, tiocb2 5, 6 7, 8 i/o input capture/ output compare match a2 and b2: the tgr2a and tgr2b input capture input or output compare output, or pwm output pins. tioca3, tiocb3, tiocc3, tiocd3 54 to 56, 59 56 to 58, 61 i/o input capture/ output compare match a3 to d3: the tgr3a to tgr3d input capture input or output compare output, or pwm output pins. tioca4, tiocb4 89, 90 91, 92 i/o input capture/ output compare match a4 and b4: the tgr4a and tgr4b input capture input or output compare output, or pwm output pins. tioca5, tiocb5 91, 92 93, 94 i/o input capture/ output compare match a5 and b5: the tgr5a and tgr5b input capture input or output compare output, or pwm output pins. 8-bit timer tmo0, tmo1 91, 92 93, 94 output compare match output: the compare match output pins. tmci0, tmci1 59, 90 61, 92 input counter external clock input: input pins for the external clock input to the counter. tmri0, tmri1 56, 89 58, 91 input counter external reset input: the counter reset input pins. watchdog timer (wdt) wdtovf
18 pin no. type symbol tfp-100b fp-100a i/o name and function serial communication txd1, txd0 9, 8 11, 10 output transmit data (channel 0, 1): data output pins. interface (sci) smart card rxd1, rxd0 11, 10 13, 12 input receive data (channel 0, 1): data input pins. interface sck1 sck0 13, 12 15, 14 i/o serial clock (channel 0, 1): clock i/o pins. a/d converter an7 to an0 86 to 79 88 to 81 input analog 7 to 0: analog input pins. adtrg
19 pin no. type symbol tfp-100b fp-100a i/o name and function i/o ports p35 to p30 13 to 8 15 to 10 i/o port 3: a 6-bit i/o port. input or output can be designated for each bit by means of the port 3 data direction register (p3ddr). p47 to p40 86 to 79 88 to 81 input port 4: an 8-bit input port. pa3 to pa0 53 to 50 55 to 52 i/o port a * 4 : a 4-bit i/o port. input or output can be designated for each bit by means of the port a data direction register (paddr). pb7 to pb0 48 to 41 50 to 43 i/o port b * 4 : an 8-bit i/o port. input or output can be designated for each bit by means of the port b data direction register (pbddr). pc7 to pc0 39 to 32 41 to 34 i/o port c * 4 : an 8-bit i/o port. input or output can be designated for each bit by means of the port c data direction register (pcddr). pd7 to pd0 30 to 23 32 to 25 i/o port d * 4 : an 8-bit i/o port. input or output can be designated for each bit by means of the port d data direction register (pdddr). pe7 to pe0 22 to 19, 17 to 14 24 to 21, 19 to 16 i/o port e: an 8-bit i/o port. input or output can be designated for each bit by means of the port e data direction register (peddr). pf7 to pf0 69 to 76 71 to 78 i/o port f: an 8-bit i/o port. input or output can be designated for each bit by means of the port f data direction register (pfddr). pg4 to pg0 97 to 93 99 to 95 i/o port g: a 5-bit i/o port. input or output can be designated for each bit by means of the port g data direction register (pgddr). notes: 1. applies to the h8s/2318 f-ztat and h8s/2315 f-ztat versions only. 2. applies to the h8s/2319 f-ztat version only. 3. applies to mask rom and romless versions only. 4. cannot be used as an i/o port on the romless versions.
20 1.6 product lineup table 1.4 h8s/2319, h8s/2318 series product lineup product type model marking package (hitachi package code) h8s/2319 * 1 f-ztat version hd64f2319 hd64f2319vte 100-pin tqfp (tfp-100b) hd64f2319vf 100-pin qfp (fp-100a) h8s/2318 mask rom version hd6432318 * 2 hd6432318te 100-pin tqfp (tfp-100b) hd6432318f 100-pin qfp (fp-100a) f-ztat version hd64f2318 hd64f2318vte 100-pin tqfp (tfp-100b) hd64f2318vf 100-pin qfp (fp-100a) h8s/2317 mask rom version hd6432317 * 2 hd6432317te 100-pin tqfp (tfp-100b) hd6432317f 100-pin qfp (fp-100a) h8s/2316 * 1 mask rom version hd6432316 hd6432316te 100-pin tqfp (tfp-100b) hd6432316f 100-pin qfp (fp-100a) h8s/2315 * 1 f-ztat version hd64f2315 hd64f2315vte 100-pin tqfp (tfp-100b) hd64f2315vf 100-pin qfp (fp-100a) h8s/2313 * 1 mask rom version hd6432313 hd6432313te 100-pin tqfp (tfp-100b) hd6432313f 100-pin qfp (fp-100a) h8s/2312 romless version hd6412312 hd6412312vte 100-pin tqfp (tfp-100b) hd6412312vf 100-pin qfp (fp-100a) h8s/2311 mask rom version hd6432311 hd6432311te 100-pin tqfp (tfp-100b) hd6432311f 100-pin qfp (fp-100a) h8s/2310 romless version hd6412310 hd6412310vte 100-pin tqfp (tfp-100b) hd6412310vf 100-pin qfp (fp-100a) notes: 1. under development 2. the hd6432318 and hd6432317 include products for v cc = 2.4 v to 3.6 v (low-voltage operation) as well as for v cc = 2.7 v to 3.6 v and v cc = 3.0 v to 3.6 v. for details, see section 7, electrical characteristics.
21 1.7 package dimensions hitachi code jedec eiaj weight (reference value) tfp-100b conforms 0.5 g unit: mm *dimension including the plating thickness base material dimension 16.0 8 figure 1.4 tfp-100b package dimensions
22 hitachi code jedec eiaj weight (reference value) fp-100a 1.7 g unit: mm *dimension including the plating thickness base material dimension 0.13 m 0 10 0.20 0.58 0.83 0.30 figure 1.5 fp-100a package dimensions
23 section 2 mcu operating modes 2.1 overview 2.1.1 operating mode selection (h8s/2318 f-ztat and h8s/2315 f-ztat versions) the h8s/2318 series has eight operating modes (modes 4 to 7, 10, 11, 14 and 15). these modes are determined by the mode pin (md2 to md0) and flash write enable pin (fwe) settings. the cpu operating mode and initial bus width can be selected as shown in table 2.1. table 2.1 lists the mcu operating modes. table 2.1 mcu operating mode selection (h8s/2318 f-ztat and h8s/2315 f-ztat versions) mcu cpu external data bus operating mode fwe md2 md1 md0 operating mode description on-chip rom initial value max. value 0 0000 11 210 31 4 1 0 0 advanced expanded mode with disabled 16 bits 16 bits 51 on-chip rom disabled 8 bits 16 bits 6 1 0 expanded mode with on-chip rom enabled enabled 8 bits 16 bits 7 1 single-chip mode 8 1000 91 10 1 0 advanced boot mode enabled 8 bits 16 bits 11 1 12 100 13 1 14 1 0 advanced user program mode enabled 8 bits 16 bits 15 1
24 the cpu's architecture allows for 4 gbytes of address space, but the h8s/2318 series actually accesses a maximum of 16 mbytes. modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the external expansion modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. note that the functions of each pin depend on the operating mode. modes 10, 11, 14, and 15 are boot modes and user program modes in which the flash memory can be programmed and erased. for details, see section 17, rom, in the hardware manual the h8s/2318 series can only be used in modes 4 to 7, 10, 11, 14, and 15. this means that the flash write enable pin and mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 2.1.2 operating mode selection (mask rom, romless, and h8s/2319 f-ztat versions) the h8s/2319 and h8s/2318 series have four operating modes (modes 4 to 7). the operating mode is determined by the mode pins (md2 to md0). the cpu operating mode, enabling or disabling of on-chip rom, and the initial bus width setting can be selected as shown in table 2.2. table 2.2 lists the mcu operating modes.
25 table 2.2 mcu operating mode selection (mask rom, romless, and h8s/2319 f-ztat versions) mcu cpu external data bus operating mode md2 md1 md0 operating mode description on-chip rom initial value max. value 0 000 11 210 31 4 * 1 0 0 advanced expanded mode with disabled 16 bits 16 bits 5 * 1 on-chip rom disabled 8 bits 16 bits 6 1 0 expanded mode with on-chip rom enabled enabled 8 bits 16 bits 7 1 single-chip mode note: * only modes 4 and 5 are provided in the romless version. the cpu's architecture allows for 4 gbytes of address space, but the h8s/2319 and h8s/2318 series actually access a maximum of 16 mbytes. modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the external expansion modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. note that the functions of each pin depend on the operating mode. the h8s/2319 and h8s/2318 series can only be used in modes 4 to 7. this means that the mode pins must be set to select one of these modes. however, note that only mode 4 or 5 can be set for the romless version. do not change the inputs at the mode pins during operation. 2.1.3 register configuration the h8s/2319 and h8s/2318 series have a mode control register (mdcr) that indicates the inputs at the mode pins (md2 to md0), and a system control register (syscr) and system control register 2 (syscr2)* 2 that control the operation of the chip. table 2.3 summarizes these registers.
26 table 2.3 registers name abbreviation r/w initial value address * 1 mode control register mdcr r undefined h'ff3b system control register syscr r/w h'01 h'ff39 system control register 2 * 2 syscr2 r/w h'00 h'ff42 notes: 1. lower 16 bits of the address. 2. the syscr2 register can only be used in the f-ztat version. in the mask rom and romless versions this register will return an undefined value if read, and cannot be modified. 2.2 register descriptions 2.2.1 mode control register (mdcr) bit:7 65 43 21 0 mds2 mds1 mds0 initial value : 1 0 0 0 0 * * * r/w: r r r note: * determined by pins md2 to md0. mdcr is an 8-bit read-only register that indicates the current operating mode of the h8s/2318 series chip. bit 7?eserved: this bit is always read as 1, and cannot be modified. bits 6 to 3?eserved: these bits are always read as 0, and cannot be modified. bits 2 to 0?ode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to pins md2 to md0. mds2 to mds0 are read-only bits, and cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a reset. 2.2.2 system control register (syscr) bit:7 65 43 21 0 intm1 intm0 nmieg lwrod rame initial value : 0 0 0 0 0 0 0 1 r/w : r/w r/w r/w r/w r/w r/w r/w
27 bit 7?eserved: only 0 should be written to this bit. bit 6?eserved: this bit is always read as 0, and cannot be modified. bits 5 and 4?nterrupt control mode 1 and 0 (intm1, intm0): these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 3.4.1, interrupt control modes and interrupt operation, in the hardware manual. bit 5 intm1 bit 4 intm0 interrupt control mode description 0 0 0 control of interrupts by i bit (initial value) 1 setting prohibited 1 0 2 control of interrupts by i2 to i0 bits and ipr 1 setting prohibited bit 3?mi edge select (nmieg): selects the valid edge of the nmi interrupt input. bit 3 nmieg description 0 an interrupt is requested at the falling edge of nmi input (initial value) 1 an interrupt is requested at the rising edge of nmi input bit 2?wr output disable (lwrod): enables or disables lwr output. bit 2 lwrod description 0 pf3 is designated as lwr output pin (initial value) 1 pf3 is designated as i/o port, and does not function as lwr output pin bit 1?eserved: only 0 should be written to this bit. bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value)
28 2.2.3 system control register 2 (syscr2) (f-ztat version only) bit:7 65 43 21 0 flshe initial value : 0 0 0 0 0 0 0 0 r/w : r/w syscr2 is an 8-bit readable/writable register that performs on-chip flash memory control. syscr2 is initialized to h'00 by a reset, and in hardware standby mode. bits 7 to 4?eserved: these bits are always read as 0, and cannot be modified. bit 3?lash memory control register enable (flshe): controls cpu access to the flash memory control registers (flmcr1, flmcr2, ebr1, and ebr2). for details, see section 17, rom, in the hardware manual. bit 3 flshe description 0 flash control registers are not selected for addresses h'ffffc8 to h'ffffcb (initial value) 1 flash control registers are selected for addresses h'ffffc8 to h'ffffcb bits 2 to 0?eserved: these bits are always read as 0, and cannot be modified. 2.3 operating mode descriptions 2.3.1 modes 1 to 3 modes 1 to 3 are not supported in the h8s/2319 and h8s/2318 series, and must not be set. 2.3.2 mode 4 (expanded mode with on-chip rom disabled) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins p13 to p10, ports a, b, and c function as an address bus, ports d and e functions as a data bus, and part of port f carries bus control signals. pins p13 to p10 function as input ports immediately after a reset. these pins can be set to output addresse by setting the corresponding data direction register (ddr) bits and a23e to a20e in pfcr1 to 1.
29 the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 2.3.3 mode 5 (expanded mode with on-chip rom disabled) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins p13 to p10, ports a, b and c function as an address bus, port d functions as a data bus, and part of port f carries bus control signals. pins p13 to p10 function as input ports immediately after a reset. these pins can be set to output addresses by setting the corresponding data direction register (ddr) bits and a23e to a20e in pfcr1 to 1. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. 2.3.4 mode 6 (expanded mode with on-chip rom enabled) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. pins p13 to p10, ports a, b, and c function as input ports immediately after a reset. these pins can be set to output addresses by setting the corresponding data direction register (ddr) bits and a23e to a20e in pfcr1 to 1. port d functions as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. 2.3.5 mode 7 (single-chip mode) the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input/output ports. 2.3.6 modes 8 and 9 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only) modes 8 and 9 are not supported in the h8s/2319 and h8s/2318 series, and must not be set.
30 2.3.7 mode 10 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only) this is a flash memory boot mode. for details, see section 17, rom, in the hardware manual. except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip rom enabled. 2.3.8 mode 11 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only) this is a flash memory boot mode. for details, see section 17, rom, in the hardware manual. except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode. 2.3.9 modes 12 and 13 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only) modes 12 and 13 are not supported in the h8s/2319 and h8s/2318 series, and must not be set. 2.3.10 mode 14 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only) this is a flash memory user program mode. for details, see section 17, rom, in the hardware manual. except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip rom enabled. 2.3.11 mode 15 (h8s/2318 f-ztat and h8s/2315 f-ztat versions only) this is a flash memory user program mode. for details, see section 17, rom, in the hardware manual. except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode.
31 2.4 pin functions in each operating mode the pin functions of ports 1 and a to f vary depending on the operating mode. table 2.4 shows their functions in each operating mode. table 2.4 pin functions in each mode port mode 4 mode 5 mode 6 * 2 mode 10 * 3 mode 14 * 3 mode 7 * 2 mode 11 * 3 mode 15 * 3 port 1 p13 to p10 p * 1 /t/a p * 1 /t/a p * 1 /t/a p * 1 /t port a pa3 to pa0 a a p * 1 /a p port b a a p * 1 /a p port c a a p * 1 /a p port d d d d p port e p/d * 1 p * 1 /d p * 1 /d p port f pf7 p/c * 1 p/c * 1 p/c * 1 p * 1 /c pf6, pf3 p/c * 1 p/c * 1 p/c * 1 p pf5, pf4 c c c pf2 to pf0 p * 1 /c p * 1 /c p * 1 /c legend p: i/o port t: timer i/o a: address bus output d: data bus i/o c: control signals, clock i/o notes: 1. after reset 2. not used on romless version. 3. applies to h8s/2318 f-ztat and h8s/2315 f-ztat versions only. 2.5 memory map in each operating mode figures 2.1 to 2.7 show memory maps for each of the operating modes. the address space is 16 mbytes. the address space is divided into eight areas.
32 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space external address space on-chip rom on-chip ram * 3 reserved area * 4 on-chip ram * 3, * 6 reserved area * 4 on-chip ram * 6 reserved area * 4 notes: 1. external addresses when eae = 1 in bcrl; on-chip rom when eae = 0. 2. reserved area when eae = 1 in bcrl; on-chip rom when eae = 0. 3. external addresses can be accessed by clearing the rame bit in syscr to 0. 4. do not access the reserved area in addresses h'ff7400 to h'ffdbff. 5. do not access the reserved areas. 6. when writing to the flash memory, do not clear the rame bit in syscr to 0 because the on-chip ram is used in the writing procedure. internal i/o registers on-chip rom on-chip rom/ reserved area * 2, * 5 external address space external address space internal i/o registers external address space internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'000000 h'080000 h'fffc00 h'ffdc00 h'ffffff h'ff7400 h'ff7400 h'ff7400 h'080000 h'fffbff h'ffdc00 h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 on-chip rom/ external address space * 1 h'fffe50 h'010000 h'010000 h'07ffff h'fffc00 h'ffdc00 h'ffffff h'ffff08 h'ffff28 h'fffe50 figure 2.1 h8s/2319 f-ztat memory map in each operating mode
33 modes 4 and 5 * 1 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * 4 notes: 1. only modes 4 and 5 are provided in the romless version (h8s/2312). 2. external addresses when eae = 1 in bcrl; on-chip rom when eae = 0. 3. reserved area when eae = 1 in bcrl; on-chip rom when eae = 0. 4. external addresses can be accessed by clearing the rame bit in syscr to 0. 5. do not access the reserved areas. internal i/o registers on-chip rom on-chip rom/ reserved area * 3, * 5 external address space external address space internal i/o registers external address space on-chip ram * 4 on-chip ram internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'000000 h'040000 h'fffc00 h'ffffff h'ffdc00 h'ffdc00 h'ffdc00 h'fffbff h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 on-chip rom/ external address space * 2 h'fffe50 h'010000 h'010000 h'03ffff h'fffc00 h'ffffff h'ffff08 h'ffff28 h'fffe50 figure 2.2 (a) h8s/2318 and h8s/2312 memory map in each operating mode
34 mode 10 boot mode (advanced expanded mode with on-chip rom enabled) mode 11 boot mode (advanced single-chip mode) on-chip rom on-chip rom external address space on-chip ram * 3 on-chip ram * 3 on-chip rom/ reserved area * 2, * 4 internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'040000 h'03ffff h'ffdc00 h'fffbff h'ffffff h'fffe50 h'ffff07 h'ffff28 on-chip rom/ external address space * 1 h'010000 h'010000 h'ffdc00 h'fffc00 h'fffe50 h'ffffff h'ffff08 h'ffff28 notes: 1. external addresses when eae = 1 in bcrl; on-chip rom when eae = 0. 2. reserved area when eae = 1 in bcrl; on-chip rom when eae = 0. 3. on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. 4. do not access the reserved areas. figure 2.2 (b) h8s/2318 memory map in each operating mode (f-ztat version only)
35 mode 14 user program mode (advanced expanded mode with on-chip rom enabled) mode 15 user program mode (advanced single-chip mode) on-chip rom on-chip rom external address space on-chip ram * 3 on-chip ram * 3 on-chip rom/ reserved area * 2, * 4 internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'040000 h'03ffff h'ffdc00 h'fffbff h'ffffff h'fffe50 h'ffff07 h'ffff28 on-chip rom/ external address space * 1 h'010000 h'010000 h'ffdc00 h'fffc00 h'fffe50 h'ffffff h'ffff08 h'ffff28 notes: 1. external addresses when eae = 1 in bcrl; on-chip rom when eae = 0. 2. reserved area when eae = 1 in bcrl; on-chip rom when eae = 0. 3. on-chip ram is used for flash memory programming. do not clear the rame bit in syscr to 0. 4. do not access the reserved areas. figure 2.2 (c) h8s/2318 memory map in each operating mode (f-ztat version only)
36 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * 3 notes: 1. external addresses when eae = 1 in bcrl; on-chip rom or reserved area when eae = 0. 2. reserved area when eae = 1 in bcrl; on-chip rom eae = 0. 3. external addresses can be accessed by clearing the rame bit in syscr to 0. 4. do not access the reserved areas. internal i/o registers on-chip rom on-chip rom/ reserved area * 2, * 4 external address space external address space internal i/o registers external address space on-chip ram * 3 on-chip ram internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'000000 h'040000 h'fffc00 h'ffffff h'ffdc00 h'ffdc00 h'ffdc00 h'fffbff h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 on-chip rom/ external address space * 1 reserved area * 4 reserved area * 4 /external address space * 1 h'fffe50 h'010000 h'010000 h'020000 h'020000 h'03ffff h'fffc00 h'ffffff h'ffff08 h'ffff28 h'fffe50 figure 2.3 h8s/2317 memory map in each operating mode
37 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * 2 notes: 1. external addresses when eae = 1 in bcrl; reserved area when eae = 0. 2. external addresses can be accessed by clearing the rame bit in syscr to 0. 3. do not access the reserved areas. internal i/o registers on-chip rom reserved area * 3 external address space external address space internal i/o registers external address space on-chip ram * 2 on-chip ram internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'000000 h'040000 h'fffc00 h'ffffff h'ffdc00 h'ffdc00 h'ffdc00 h'fffbff h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 reserved area * 3 / external address space * 1 h'fffe50 h'010000 h'010000 h'03ffff h'fffc00 h'ffffff h'ffff08 h'ffff28 h'fffe50 figure 2.4 h8s/2316 memory map in each operating mode
38 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space external address space on-chip rom on-chip ram * 3 on-chip ram * 3 reserved area * 4 reserved area * 4 reserved area * 4 on-chip ram notes: 1. external addresses when eae = 1 in bcrl; on-chip rom when eae = 0. 2. reserved area when eae = 1 in bcrl; on-chip rom when eae = 0. 3. external addresses can be accessed by clearing the rame bit in syscr to 0. 4. do not access the reserved area in addresses h'060000 to h'07ffff. 5. do not access the reserved areas. internal i/o registers on-chip rom on-chip rom/ reserved area * 2, * 5 external address space external address space internal i/o registers external address space internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'000000 h'080000 h'fffc00 h'ffdc00 h'ffffff h'080000 h'060000 h'060000 h'060000 h'fffbff h'ffdc00 h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 on-chip rom/ external address space * 1 h'fffe50 h'010000 h'010000 h'07ffff h'fffc00 h'ffdc00 h'ffffff h'ffff08 h'ffff28 h'fffe50 figure 2.5 (a) h8s/2315 f-ztat memory map in each operating mode
39 mode 10 boot mode (advanced expanded mode with on-chip rom enabled) mode 11 boot mode (advanced single-chip mode) on-chip rom/ external address space * 1 external address space on-chip ram * 3 reserved area * 4 reserved area * 4 on-chip ram * 3 internal i/o registers on-chip rom on-chip rom on-chip rom/ reserved area * 2, * 5 external address space internal i/o registers external address space internal i/o registers internal i/o registers h'000000 h'000000 h'fffc00 h'ffdc00 h'ffffff h'080000 h'060000 h'060000 h'010000 h'fffbff h'ffdc00 h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 h'fffe50 h'010000 h'07ffff notes: 1. external addresses when eae = 1 in bcrl; on-chip rom when eae = 0. 2. reserved area when eae = 1 in bcrl; on-chip rom when eae = 0. 3. external addresses can be accessed by clearing the rame bit in syscr to 0. 4. do not access the reserved area in addresses h'060000 to h'07ffff. 5. do not access the reserved areas. figure 2.5 (b) h8s/2315 f-ztat memory map in each operating mode
40 mode 14 user program mode (advanced expanded mode with on-chip rom enabled) mode 15 user program mode (advanced single-chip mode) on-chip rom/ external address space * 1 external address space on-chip ram * 3 reserved area * 4 reserved area * 4 on-chip ram * 3 internal i/o registers on-chip rom on-chip rom on-chip rom/ reserved area * 2, * 5 external address space internal i/o registers external address space internal i/o registers internal i/o registers h'000000 h'000000 h'fffc00 h'ffdc00 h'ffffff h'080000 h'060000 h'060000 h'010000 h'fffbff h'ffdc00 h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 h'fffe50 h'010000 h'07ffff notes: 1. external addresses when eae = 1 in bcrl; on-chip rom when eae = 0. 2. reserved area when eae = 1 in bcrl; on-chip rom when eae = 0. 3. external addresses can be accessed by clearing the rame bit in syscr to 0. 4. do not access the reserved area in addresses h'060000 to h'07ffff. 5. do not access the reserved areas. figure 2.5 (c) h8s/2315 f-ztat memory map in each operating mode
41 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * 2 notes: 1. external addresses when eae = 1 in bcrl; reserved area when eae = 0. 2. external addresses can be accessed by clearing the rame bit in syscr to 0. 3. do not access the reserved areas. internal i/o registers on-chip rom reserved area * 3 external address space external address space internal i/o registers external address space on-chip ram * 2 on-chip ram reserved area * 3 internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'000000 h'040000 h'fffc00 h'ffffff h'ffdc00 h'ffdc00 h'ffdc00 h'fffbff h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 reserved area * 3 / external address space * 1 h'fffe50 h'010000 h'010000 h'fff400 reserved area * 3 h'fff400 reserved area * 3 h'fff400 h'03ffff h'fffc00 h'ffffff h'ffff08 h'ffff28 h'fffe50 figure 2.6 h8s/2313 memory map in each operating mode
42 modes 4 and 5 * 1 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * 3 notes: 1. only modes 4 and 5 are provided in the romless version (h8s/2310). 2. external addresses when eae = 1 in bcrl; reserved area when eae = 0. 3. external addresses can be accessed by clearing the rame bit in syscr to 0. 4. do not access the reserved areas. internal i/o registers on-chip rom reserved area * 4 reserved area * 4 reserved area * 4 external address space external address space internal i/o registers external address space on-chip ram * 3 on-chip ram reserved area * 4 internal i/o registers external address space internal i/o registers internal i/o registers internal i/o registers external address space h'000000 h'000000 h'000000 h'040000 h'fffc00 h'ffffff h'ffdc00 h'ffdc00 h'ffdc00 h'fffbff h'ffffff h'ffff08 h'fffe50 h'ffff07 h'ffff28 h'ffff28 reserved area * 4 / external address space * 2 h'fffe50 h'010000 h'010000 h'fff400 reserved area * 4 h'fff400 reserved area * 4 h'fff400 h'008000 h'008000 h'03ffff h'fffc00 h'ffffff h'ffff08 h'ffff28 h'fffe50 figure 2.7 h8s/2311 and h8s/2310 memory map in each operating mode
43 section 3 exception handling and interrupt controller 3.1 overview 3.1.1 exception handling types and priority as table 3.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 3.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits in syscr. for details of exception handling and the interrupt controller, see section 2, exception handling, and section 3, interrupt controller, in the hardware manual. table 3.1 exception types and priority priority exception type start of exception handling high reset starts after a low-to-high transition at the res pin, or when the watchdog timer overflows trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 low trap instruction * 3 (trapa) started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in the program execution state.
44 3.2 interrupt controller 3.2.1 interrupt controller features ? two interrupt control modes ? either of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with iprs ? interrupt priority registers (iprs) are provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. ? nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? nine external interrupt pins ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. ? falling edge, rising edge, or both edge detection, or level sensing, can be selected independently for irq7 to irq0. ? dtc control ? dtc activation is controlled by means of interrupts. 3.2.2 pin configuration table 3.2 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 7 to 0 irq7 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected
45 3.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq7 to irq0) and internal interrupts (43 sources). 3.3.1 external interrupts there are nine external interrupts: nmi and irq7 to irq0. nmi and irq7 to irq0 can be used to restore the chip from software standby mode. (irq7 to irq3 can be used as software standby mode clearing sources by setting the irq37s bit in sbycr to 1.) nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. interrupts irq7 to irq0: interrupts irq7 to irq0 are requested by an input signal at pins irq7 to irq0 . interrupts irq7 to irq0 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq7 to irq0 . ? enabling or disabling of interrupt requests irq7 to irq0 can be selected with ier. ? the interrupt priority level can be set with the ipr registers. ? the status of interrupt requests irq7 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq7 to irq0 is shown in figure 3.1. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n = 7 to 0 figure 3.1 block diagram of interrupts irq7 to irq0
46 figure 3.2 shows the timing of irqnf setting. irq n input pin irqnf figure 3.2 timing of irqnf setting the vector numbers for irq7 to irq0 interrupt exception handling are 23 to 16. detection of irq7 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. when a pin is used as an external interrupt input pin, clear the corresponding ddr bit to 0 and do not use the pin as an i/o pin for another function. 3.3.2 internal interrupts there are 43 sources for internal interrupts from on-chip supporting modules. 1. for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if any one of these is set to 1, an interrupt request is issued to the interrupt controller. 2. the interrupt priority level can be set by means of the ipr registers. 3. the dtc can be activated by a tpu, sci, or other interrupt request. when the dtc is activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect. 3.3.3 interrupt exception vector table table 3.3 shows interrupt sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. the dtc can be activated by an interrupt request. priorities among modules can be set by means of the ipr registers. the situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 3.3.
47 table 3.3 interrupt sources, vector addresses, and interrupt priorities interrupt source origin of interrupt source vector number vector address * ipr priority dtc activation power-on reset 0 h'0000 high reserved 1 h'0004 reserved for system 2 h'0008 use 3 h'000c 4 h'0010 trace 5 h'0014 reserved for system use 6 h'0018 nmi external pin 7 h'001c trap instruction 8 h'0020 (4 sources) 9 h'0024 10 h'0028 11 h'002c reserved for system 12 h'0030 use 13 h'0034 14 h'0038 15 h'003c irq0 external pin 16 h'0040 ipra6 to ipra4 irq1 17 h'0044 ipra2 to ipra0 irq2 18 h'0048 iprb6 to iprb4 irq3 19 h'004c irq4 20 h'0050 iprb2 to iprb0 irq5 21 h'0054 irq6 22 h'0058 iprc6 to iprc4 irq7 23 h'005c low
48 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activation swdtend (software- activated data transfer end) dtc 24 h'0060 iprc2 to iprc0 high wovi (interval timer) watchdog timer 25 h'0064 iprd6 to iprd4 reserved 26 h'0068 iprd2 to iprd0 reserved 27 h'006c ipre6 to ipre4 adi (a/d conversion end) a/d 28 h'0070 ipre2 to ipre0 reserved 29 h'0074 30 h'0078 31 h'007c tgi0a (tgr0a input capture/compare match) tpu channel 0 32 h'0080 iprf6 to iprf4 tgi0b (tgr0b input capture/compare match) 33 h'0084 tgi0c (tgr0c input capture/compare match) 34 h'0088 tgi0d (tgr0d input capture/compare match) 35 h'008c tci0v (overflow 0) 36 h'0090 reserved 37 h'0094 38 h'0098 39 h'009c low
49 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activation tgi1a (tgr1a input capture/compare match) tpu channel 1 40 h'00a0 iprf2 to iprf0 high tgi1b (tgr1b input capture/compare match) 41 h'00a4 tci1v (overflow 1) 42 h'00a8 tci1u (underflow 1) 43 h'00ac tgi2a (tgr2a input capture/compare match) tpu channel 2 44 h'00b0 iprg6 to iprg4 tgi2b (tgr2b input capture/compare match) 45 h'00b4 tci2v (overflow 2) 46 h'00b8 tci2u (underflow 2) 47 h'00bc tgi3a (tgr3a input capture/compare match) tpu channel 3 48 h'00c0 iprg2 to iprg0 tgi3b (tgr3b input capture/compare match) 49 h'00c4 tgi3c (tgr3c input capture/compare match) 50 h'00c8 tgi3d (tgr3d input capture/compare match) 51 h'00cc tci3v (overflow 3) 52 h'00d0 reserved 53 h'00d4 54 h'00d8 55 h'00dc low
50 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activation tgi4a (tgr4a input capture/compare match) tpu channel 4 56 h'00e0 iprh6 to iprh4 high tgi4b (tgr4b input capture/compare match) 57 h'00e4 tci4v (overflow 4) 58 h'00e8 tci4u (underflow 4) 59 h'00ec tgi5a (tgr5a input capture/compare match) tpu channel 5 60 h'00f0 iprh2 to iprh0 tgi5b (tgr5b input capture/compare match) 61 h'00f4 tci5v (overflow 5) 62 h'00f8 tci5u (underflow 5) 63 h'00fc cmia0 (compare match a) 8-bit timer channel 0 64 h'0100 ipri6 to ipri4 cmib0 (compare match b) 65 h'0104 ovi0 (overflow 0) 66 h'0108 reserved 67 h'010c cmia1 (compare match a) 8-bit timer channel 1 68 h'0110 ipri2 to ipri0 cmib1 (compare match b) 69 h'0114 ovi1 (overflow 1) 70 h'0118 reserved 71 h'011c low
51 interrupt source origin of interrupt source vector number vector address * ipr priority dtc activation reserved 72 h'0120 iprj6 to iprj4 high 73 h'0124 74 h'0128 75 h'012c 76 h'0130 77 h'0134 78 h'0138 79 h'013c eri0 (receive error 0) sci channel 0 80 h'0140 iprj2 to iprj0 rxi0 (receive-data-full 0) 81 h'0144 txi0 (transmit-data- empty 0) 82 h'0148 tei0 (transmit end 0) 83 h'014c eri1 (receive error 1) sci channel 1 84 h'0150 iprk6 to iprk4 rxi1 (receive-data-full 1) 85 h'0154 txi1 (transmit-data- empty 1) 86 h'0158 tei1 (transmit end 1) 87 h'015c reserved 88 h'0160 iprk2 to iprk0 89 h'0164 90 h'0168 91 h'016c low note: * lower 16 bits of the start address.
52 3.4 interrupt control modes and interrupt operation interrupt operations in the h8s/2319 and h8s/2318 series differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bit is set to 1 are controlled by the interrupt controller. the interrupt control modes are shown in table 3.4, the interrupts selected in each interrupt control mode in tables 3.5 and 3.6, and operations and control signal functions in each interrupt control mode in table 3.7. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in the ipr registers, and the masking state indicated by the i bit in the cpu? ccr and bits i2 to i0 in exr. table 3.4 interrupt control modes interrupt control mode intm1 intm0 priority setting registers interrupt mask bits description 0 0 0 i interrupt mask control is performed by the i bit. 1 setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. 1 setting prohibited table 3.5 interrupts selected in each interrupt control mode (1) interrupt control interrupt mask bits mode i selected interrupts 0 0 all interrupts 1 nmi interrupts 2 * all interrupts * : don? care
53 table 3.6 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt with priority level greater than the mask level (ipr > i2 to i0) table 3.7 operations and control signal functions in each interrupt control mode interrupt settings interrupt acceptance control 8-level control default priority t control mode intm1 intm0 i i2 to i0 ipr determination (trace) 000 im x * 2 210x * 1 im pr t legend : interrupt operation control performed x: no operation (all interrupts enabled) im: used as interrupt mask bit pr: sets priority ? not used notes: 1. set to 1 when interrupt is accepted. 2. keep the initial setting.
54 3.5 interrupt response times the h8s/2319 and h8s/2318 series are capable of fast word access to on-chip memory, and the program area is provided in on-chip rom and the stack area in on-chip ram, enabling high- speed processing. table 3.8 shows interrupt response times?he interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution phase symbols used in table 3.8 are explained in table 3.9. table 3.8 interrupt response times advanced mode no. execution phase intm1 = 0 intm1 = 1 1 interrupt priority determination * 1 33 2 number of wait states until executing instruction ends * 2 1 to (19 + 2 ? s i ) 1 to (19 + 2 ? s i ) 3 pc, ccr, and exr stacking 2 ? s k 3 ? s k 4 vector fetch 2 ? s i 2 ? s i 5 instruction fetch * 3 2 ? s i 2 ? s i 6 internal processing * 4 22 total (when using on-chip memory) 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. table 3.9 number of states in interrupt handling routine execution phases access to external device 8-bit bus 16-bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6 + 2m 2 3 + m branch address read s j stack manipulation s k legend m: number of wait states in an external device access
55 3.6 dtc activation by interrupt 3.6.1 overview in the h8s/2319 and h8s/2318 series, the dtc can be activated by an interrupt. in this case, the following options are available: 1. interrupt request to cpu 2. activation request to dtc 3. selection of a number of the above see table 3.3 for the interrupt requests that can be used to activate the dtc. for details, see section 6, data transfer controller, in the hardware manual. 3.6.2 block diagram figure 3.3 shows a block diagram of the dtc and interrupt controller. selection circuit dtcer dtvecr control logic priority determination cpu dtc select signal irq interrupt on-chip supporting module clear signal interrupt controller i, i2 to i0 interrupt source clear signal interrupt request cpu interrupt request vector number swdte clear signal clear signal dtc activation request vector number figure 3.3 interrupt control for dtc
56 3.6.3 operation the interrupt controller has three main functions in dtc control, as described below. selection of interrupt source: for interrupt sources, it is possible to select dtc activation request or cpu interrupt request with the dtce bit in dtc registers dtcera to dtcere. after a dtc data transfer, the dtce bit can be cleared to 0 and an interrupt request sent to the cpu in accordance with the specification of the disel bit in the dtc? mrb register. when the dtc has performed the specified number of data transfers and the transfer counter value is 0, the dtce bit is cleared to 0 after the dtc data transfer and an interrupt request is sent to the cpu. determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see table 3.10, interrupt sources, dtc vector addresses, and corresponding dtces, for the respective priorities.
57 table 3.10 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address dtce * priority write to dtvecr software dtvecr h'0400 + (dtvecr [6:0]<<1) high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 irq6 22 h'042c dtcea1 irq7 23 h'042e dtcea0 adi (a/d conversion end) a/d 28 h'0438 dtceb6 tgi0a (gr0a compare match/input capture) tpu channel 0 32 h'0440 dtceb5 tgi0b (gr0b compare match/input capture) 33 h'0442 dtceb4 tgi0c (gr0c compare match/input capture) 34 h'0444 dtceb3 tgi0d (gr0d compare match/input capture) 35 h'0446 dtceb2 tgi1a (gr1a compare match/input capture) tpu channel 1 40 h'0450 dtceb1 tgi1b (gr1b compare match/input capture) 41 h'0452 dtceb0 tgi2a (gr2a compare match/input capture) tpu channel 2 44 h'0458 dtcec7 tgi2b (gr2b compare match/input capture) 45 h'045a dtcec6 low
58 interrupt source origin of interrupt source vector number vector address dtce * priority tgi3a (gr3a compare match/input capture) tpu channel 3 48 h'0460 dtcec5 high tgi3b (gr3b compare match/input capture) 49 h'0462 dtcec4 tgi3c (gr3c compare match/input capture) 50 h'0464 dtcec3 tgi3d (gr3d compare match/input capture) 51 h'0466 dtcec2 tgi4a (gr4a compare match/input capture) tpu channel 4 56 h'0470 dtcec1 tgi4b (gr4b compare match/input capture) 57 h'0472 dtcec0 tgi5a (gr5a compare match/input capture) tpu channel 5 60 h'0478 dtced5 tgi5b (gr5b compare match/input capture) 61 h'047a dtced4 cmia0 8-bit timer 64 h'0480 dtced3 cmib0 channel 0 65 h'0482 dtced2 cmia1 8-bit timer 68 h'0488 dtced1 cmib1 channel 1 69 h'048a dtced0 rxi0 (receive-data-full 0) sci 81 h'04a2 dtcee3 txi0 (transmit-data-empty 0) channel 0 82 h'04a4 dtcee2 rxi1 (receive-data-full 1) sci 85 h'04aa dtcee1 txi1 (transmit-data-empty 1) channel 1 86 h'04ac dtcee0 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0. operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. table 3.11 summarizes interrupt source selection and interrupt source clearance control according to the setting of the dtce bit of dtc registers dtcera to dtcere and the disel bit in the dtc? mrb register.
59 table 3.11 interrupt source selection and clearing control settings dtc interrupt source selection/clearing control dtce disel dtc cpu 0 * x 10 x 1 legend : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) : the relevant interrupt is used. the interrupt source is not cleared. x: the relevant bit cannot be used. * : don t care usage note: sci and a/d converter interrupt sources are cleared when the dtc reads or writes to the prescribed register, and are not dependent on the disel bit.
60
61 section 4 bus controller 4.1 overview the h8s/2319 and h8s/2318 series have an on-chip bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters?he cpu and data transfer controller (dtc). 4.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? in advanced mode, manages the external space as 8 areas of 2 mbytes ? bus specifications can be set independently for each area ? burst rom interfaces can be set ? basic bus interface ? chip select signals ( cs0 to cs7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area ? burst rom interface ? burst rom interface can be set for area 0 ? selection of 1- or 2-state burst access ? idle cycle insertion ? an idle cycle can be inserted in case of external read cycles in different areas ? an idle cycle can be inserted in case of an external write cycle immediately after an external read cycle ? bus arbitration function ? includes a bus arbiter that arbitrates bus mastership between the cpu and dtc ? other features ? external bus release function
62 4.1.2 block diagram area decoder bus controller abwcr astcr bcrh bcrl internal address bus cs0 to cs7 external bus control signals breq back breqo internal control signals wait controller wcrh wcrl bus mode signal bus arbiter dtc bus acknowledge signal cpu bus acknowledge signal dtc bus request signal cpu bus request signal wait internal data bus figure 4.1 block diagram of bus controller
63 4.1.3 pin configuration table 4.1 summarizes the pins of the bus controller. table 4.1 bus controller pins name symbol i/o function address strobe as output strobe signal indicating that address output on address bus is enabled. read rd output strobe signal indicating that external space is being read. high write hwr output strobe signal indicating that external space is to be written, and upper half (d15 to d8) of data bus is enabled. low write lwr output strobe signal indicating that external space is to be written, and lower half (d7 to d0) of data bus is enabled. chip select 0 cs0 output strobe signal indicating that area 0 is selected. chip select 1 cs1 output strobe signal indicating that area 1 is selected. chip select 2 cs2 output strobe signal indicating that area 2 is selected. chip select 3 cs3 output strobe signal indicating that area 3 is selected. chip select 4 cs4 output strobe signal indicating that area 4 is selected. chip select 5 cs5 output strobe signal indicating that area 5 is selected. chip select 6 cs6 output strobe signal indicating that area 6 is selected. chip select 7 cs7 output strobe signal indicating that area 7 is selected. wait wait input wait request signal when accessing external 3- state access space. bus request breq input request signal for release of bus to external device. bus request acknowledge back output acknowledge signal indicating that bus has been released. bus request output breqo output external bus request signal used when internal bus master accesses external space when external bus is released.
64 4.1.4 register configuration table 4.2 summarizes the registers of the bus controller. table 4.2 bus controller registers initial value name abbreviation r/w reset address * 1 bus width control register abwcr r/w h'ff/h'00 * 2 h'fed0 access state control register astcr r/w h'ff h'fed1 wait control register h wcrh r/w h'ff h'fed2 wait control register l wcrl r/w h'ff h'fed3 bus control register h bcrh r/w h'd0 h'fed4 bus control register l bcrl r/w h'3c h'fed5 notes: 1. lower 16 bits of the address. 2. determined by the mcu operating mode.
65 4.2 register descriptions 4.2.1 bus width control register (abwcr) bit:7 65 43 21 0 abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 modes 5 to 7 initial value : 1 1 1 1 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mode 4 initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w abwcr is an 8-bit readable/writable register that designates each area as either 8-bit access space or 16-bit access space. abwcr sets the data bus width for the external memory space. the bus width for on-chip memory and internal i/o registers is fixed regardless of the settings in abwcr. after a reset and in hardware standby mode, abwcr is initialized to h'ff in modes 5 to 7*, and to h'00 in mode 4. it is not initialized in software standby mode. note: * modes 6 and 7 cannot be used in the romless version. bits 7 to 0?rea 7 to 0 bus width control (abw7 to abw0): these bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. bit n abwn description 0 area n is designated for 16-bit access 1 area n is designated for 8-bit access (n = 7 to 0)
66 4.2.2 access state control register (astcr) bit:7 65 43 21 0 ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 initial value : 1 1 1 1 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w astcr is an 8-bit readable/writable register that designates each area as either 2-state access space or 3-state access space. astcr sets the number of access states for the external memory space. the number of access states for on-chip memory and internal i/o registers is fixed regardless of the settings in astcr. astcr is initialized to h'ff by a reset, and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?rea 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. wait state insertion is enabled or disabled at the same time. bit n astn description 0 area n is designated for 2-state access wait state insertion in area n external space access is disabled 1 area n is designated for 3-state access (initial value) wait state insertion in area n external space access is enabled (n = 7 to 0) 4.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable registers that select the number of program wait states for each area. program waits are not inserted in on-chip memory or internal i/o register access. wcrh and wcrl are initialized to h'ff by a reset, and in hardware standby mode. they are not initialized in software standby mode.
67 wcrh bit:7 65 43 21 0 w71 w70 w61 w60 w51 w50 w41 w40 initial value : 1 1 1 1 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bits 7 and 6?rea 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 w71 bit 6 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value) bits 5 and 4?rea 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 w61 bit 4 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value)
68 bits 3 and 2?rea 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 w51 bit 2 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value) bits 1 and 0?rea 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 w41 bit 0 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value)
69 wcrl bit:7 65 43 21 0 w31 w30 w21 w20 w11 w10 w01 w00 initial value : 1 1 1 1 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bits 7 and 6?rea 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 w31 bit 6 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value) bits 5 and 4?rea 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 w21 bit 4 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value)
70 bits 3 and 2?rea 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 w11 bit 2 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value) bits 1 and 0?rea 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 w01 bit 0 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value)
71 4.2.4 bus control register h (bcrh) bit:7 65 43 21 0 icis1 icis0 brstrm brsts1 brsts0 initial value : 1 1 0 1 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bcrh is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. bcrh is initialized to h'd0 by a reset, and in hardware standby mode. it is not initialized in software standby mode. bit 7?dle cycle insert 1 (icis1): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. bit 7 icis1 description 0 idle cycle not inserted in case of successive external read cycles in different areas. 1 idle cycle inserted in case of successive external read cycles in different areas. (initial value) bit 6?dle cycle insert 0 (icis0): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . bit 6 icis0 description 0 idle cycle not inserted in case of successive external read and external write cycles. 1 idle cycle inserted in case of successive external read and external write cycles. (initial value) bit 5?urst rom enable (brstrm): selects whether area 0 is used as a burst rom interface area. bit 5 brstrm description 0 area 0 is basic bus interface area (initial value) 1 area 0 is burst rom interface area
72 bit 4?urst cycle select 1 (brsts1): selects the number of burst cycles for the burst rom interface. bit 4 brsts1 description 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states (initial value) bit 3?urst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst access on the burst rom interface. bit 3 brsts0 description 0 max. 4 words in burst access (initial value) 1 max. 8 words in burst access bits 2 to 0?eserved: only 0 should be written to these bits. 4.2.5 bus control register l (bcrl) bit:7 65 43 21 0 brle breqoe eae waite initial value : 0 0 1 1 1 1 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bcrl is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, selection of the area partition unit, and enabling or disabling of wait pin input. bcrl is initialized to h'3c by a reset, and in hardware standby mode. it is not initialized in software standby mode. bit 7?us release enable (brle): enables or disables external bus release. bit 7 brle description 0 external bus release disabled. breq , back , and breqo pins can be used as i/o ports (initial value) 1 external bus release enabled
73 bit 6?reqo pin enable (breqoe): outputs a signal that requests the external bus master to drop the bus request signal ( breq ) in the external bus-released state or when an internal bus master performs an external space access. bit 6 breqoe description 0 breqo output disabled. breqo pin can be used as i/o port (initial value) 1 breqo output enabled bit 5?xternal address enable (eae): designates addresses h'010000 to h'03ffff* as either internal or external addresses. note: * h'010000 to h'05ffff in the h8s/2315. h'010000 to h'07ffff in the h8s/2319. description bit 5 eae h8s/2319, h8s/2318, h8s/2315 h8s/2317 h8s/2316, h8s/2313, h8s/2311 0 on-chip rom addresses h'010000 to h'01ffff are on-chip rom and addresses h'020000 to h'03ffff are reserved area * 1 reserved area * 1 1 addresses h'010000 to h'03ffff * 2 are external addresses in external expanded mode or reserved area * 1 in single-chip mode notes: 1. do not access a reserved area. 2. h'010000 to h'05ffff in the h8s/2315. h'010000 to h'07ffff in the h8s/2319. bits 4 to 2?eserved: only 1 should be written to these bits. bit 1?eserved: only 0 should be written to this bit. bit 0?ait pin enable (waite): selects enabling or disabling of wait input by the wait pin. bit 0 waite description 0 wait input by wait pin disabled. wait pin can be used as i/o port (initial value) 1 wait input by wait pin enabled
74 4.3 overview of bus control 4.3.1 area partitioning in advanced mode, the bus controller partitions the 16-mbyte address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. figure 4.2 shows an outline of the memory map. chip select signals ( cs0 to cs7 ) can be output for each area. area 0 (2 mbytes) h'000000 h'ffffff h'1fffff h'200000 area 1 (2 mbytes) h'3fffff h'400000 area 2 (2 mbytes) h'5fffff h'600000 area 3 (2 mbytes) h'7fffff h'800000 area 4 (2 mbytes) h'9fffff h'a00000 area 5 (2 mbytes) h'bfffff h'c00000 area 6 (2 mbytes) h'dfffff h'e00000 area 7 (2 mbytes) advanced mode figure 4.2 area partitioning
75 4.3.2 bus specifications the external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is always set. when the burst rom interface is selected, 16-bit bus mode is always set. number of access states: two or three access states can be selected with astcr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. with the burst rom interface, the number of access states may be determined without regard to astcr. when 2-state access space is designated, wait insertion is disabled. number of program wait states: when 3-state access space is designated by astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 4.3 shows the bus specifications for each basic bus interface area.
76 table 4.3 bus specifications for each area (basic bus interface) abwcr astcr wcrh, wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 00 16 2 0 100 3 0 11 10 2 13 10 82 0 100 3 0 11 10 2 13 4.3.3 memory interfaces the memory interfaces of the h8s/2319 and h8s/2318 series comprise a basic bus interface that allows direct connection of rom, sram, and so on; and a burst rom interface that allows direct connection of burst rom(only area 0). an area for which the basic bus interface is designated functions as normal space, and an area for which the burst rom interface is designated functions as burst rom space. 4.3.4 advanced mode the initial state of each area is basic bus interface, 3-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the sections on each memory interface (4.4 and 4.5) should be referred to for further details. area 0: area 0 includes on-chip rom, and in expanded mode with on-chip rom disabled, all of area 0 is external space. in expanded mode with on-chip rom enabled, the space excluding on- chip rom is external space. when area 0 external space is accessed, the cs0 signal can be output. either basic bus interface or burst rom interface can be selected for area 0. areas 1 to 6: in external expanded mode, all of area 1 to area 6 is external space.
77 when area 1 to 6 external space is accessed, the cs1 to cs6 pin signals can be output, respectively. only the basic bus interface can be used for areas 1 to 6. area 7: area 7 includes the on-chip ram and internal/o registers. in external expanded mode, the space excluding the on-chip ram and internal/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space . when area 7 external space is accessed, the cs7 signal can be output. only the basic bus interface can be used for the area 7 memory interface. 4.3.5 chip select signals the chip can output chip select signals ( cs0 to cs7 ) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. figure 4.3 shows an example of csn (n = 0 to 7) output timing. enabling or disabling of csn signal output is performed by setting the data direction register (ddr) bit for the port corresponding to the particular csn pin. in expanded mode with on-chip rom disabled, the cs0 pin is placed in the output state after a reset. pins cs1 to cs7 are placed in the input state after a reset, and so the corresponding ddr bits should be set to 1 when outputting signals cs1 to cs7 . in expanded mode with on-chip rom enabled, pins cs0 to cs7 are all placed in the input state after a reset, and so the corresponding ddr bits should be set to 1 when outputting signals cs0 to cs7 . for details, see section 5, i/o ports.
78 bus cycle t 1 t 2 t 3 area n external address address bus csn figure 4.3 csn signal output timing (n = 0 to 7)
79 4.4 basic bus interface 4.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl. for details, see section 4.4, basic bus interface, in the hardware manual. 4.4.2 wait control when accessing external space , the chip can extend the bus cycle by inserting one or more wait states (t w ). there are two ways of inserting wait states: program wait insertion and pin wait insertion using the wait pin. program wait insertion: from 0 to 3 wait states can be inserted automatically between the t 2 state and t 3 state on an individual area basis in 3-state access space, according to the settings in wcrh and wcrl. pin wait insertion: setting the waite bit in bcrl to 1 enables wait input by means of the wait pin. when external space is accessed in this state, a program wait is first inserted in accordance with the settings in wcrh and wcrl. if the wait pin is low at the falling edge of in the last t 2 or t w state, another t w state is inserted. if the wait pin is held low, t w states are inserted it goes high. this is useful when inserting four or more t w states, or when changing the number of t w states for different external devices. the waite bit setting applies to all areas. figure 4.4 shows an example of wait state insertion timing.
80 by program wait t 1 address bus as rd hwr lwr wait wait wait figure 4.4 example of wait state insertion timing the settings after a reset are: 3-state access, 3 program wait state insertion, and wait input disabled.
81 4.5 burst rom interface 4.5.1 overview with the h8s/2319 and h8s/2318 series, external space area 0 can be designated as burst rom space, and burst rom interfacing performed. the burst rom space interface enables 16-bit rom with burst access capability to be accessed at high speed. area 0 can be designated as burst rom space by means of the brstrm bit in bcrh. consecutive burst accesses of a maximum or 4 words or 8 words can be performed for cpu instruction fetches only. one or two states can be selected for burst access. 4.5.2 basic timing the number of states in the initial cycle (full access) of the burst rom interface is determined by the setting of the ast0 bit in astcr. when the ast0 bit is set to 1, wait state insertion is also possible. one or two states can be selected for the burst cycle, according to the setting of the brsts1 bit in bcrh. wait states cannot be inserted. when area 0 is designated as burst rom space, it functions as 16-bit access space regardless of the setting of the abw0 bit in abwcr. when the brsts0 bit in bcrh is cleared to 0, burst access of up to 4 words is performed; when the brsts0 bit is set to 1, burst access of up to 8 words is performed. the basic access timing for burst rom space is shown in figures 4.5 (a) and (b). the timing shown in figure 4.5 (a) is for the case where the ast0 and brsts1 bits are both set to 1, and that in figure 4.5 (b) is for the case where both these bits are cleared to 0.
82 t 1 address bus cs0 as rd figure 4.5 (a) example of burst rom access timing (when ast0 = brsts1= 1)
83 t 1 address bus cs0 as rd figure 4.5 (b) example of burst rom access timing (when ast0 = brsts1 = 0) 4.5.3 wait control as with the basic bus interface, either program wait insertion or pin wait insertion using the wait pin can be used in the initial cycle (full access) on the burst rom interface. see section 4.4.2, wait control. wait states cannot be inserted in a burst cycle.
84 4.6 idle cycle 4.6.1 operation when the h8s/2319 or h8s/2318 series chip accesses external space, it can insert a 1-state idle cycle (t i ) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, etc., with a long output floating time, and high-speed memory, i/o interfaces, and so on. consecutive reads in different areas: if consecutive reads in different areas occur while the icis1 bit in bcrh is set to 1, an idle cycle is inserted at the start of the second read cycle. this is enabled in advanced mode. figure 4.6 shows an example of the operation in this case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a read cycle for sram, each being located in a different area. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision (a) idle cycle not inserted (icis1 = 0) t 1 address bus rd (b) idle cycle inserted (icis1 = 1 (initial value)) t 2 cs cs cs cs figure 4.6 example of idle cycle operation (1)
85 write after read: if an external write occurs after an external read while the icis0 bit in bcrh is set to 1, an idle cycle is inserted at the start of the write cycle. figure 4.7 shows an example of the operation in this case. in this example, bus cycle a is a read cycle for rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in bus cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision (a) idle cycle not inserted (icis0 = 0) t 1 address bus rd (b) idle cycle inserted (icis0 = 1 (initial value)) t 2 hwr hwr cs cs cs cs figure 4.7 example of idle cycle operation (2)
86 relationship between chip select ( cs ) signal and read ( rd ) signal: depending on the system? load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 4.8. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset release, idle cycle insertion (b) is set. t 1 address bus rd cs rd (a) idle cycle not inserted (icis1 = 0) t 1 address bus bus cycle a t 2 t 3 t i t 1 bus cycle b (b) idle cycle inserted (icis1 = 1 (initial value)) t 2 cs cs rd cs cs figure 4.8 relationship between chip select ( cs ) and read ( rd )
87 4.6.2 pin states in idle cycle table 4.4 shows the pin states in an idle cycle. table 4.4 pin states in idle cycle pins pin state a23 to a0 contents of following bus cycle d15 to d0 high impedance csn as rd hwr lwr 4.7 bus release 4.7.1 overview the h8s/2319 and h8s/2318 series can release the external bus in response to a bus request from an external device. in the external bus-released state, the internal bus master continues to operate as long as there is no external access. if an internal bus master wants to make an external access in the external bus-released state, it can issue a request off-chip for the bus request to be dropped. 4.7.2 operation in external expanded mode, the bus can be released to an external device by setting the brle bit in bcrl to 1. driving the breq pin low issues an external bus request to the h8s/2319 or h8s/2318 series chip. when the breq pin is sampled, at the prescribed timing the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high- impedance state, establishing the external bus-released state. in the external bus-released state, an internal bus master can perform accesses using the internal bus. when an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped.
88 if the breqoe bit in bcrl is set to 1, when an internal bus master wants to make an external access in the external bus-released state, the breqo pin is driven low and a request can be made off-chip to drop the bus request. when the breq pin goes high, the back pin is driven high at the prescribed timing and the external bus-released state is terminated. if an external bus release request and external access occur simultaneously, the order of priority is as follows: (high) external bus release > internal bus master external access (low) 4.7.3 pin states in external-bus-released state table 4.5 shows pin states in the external-bus-released state. table 4.5 pin states in bus-released state pins pin state a23 to a0 high impedance d15 to d0 high impedance csn as rd hwr lwr
89 4.7.4 transition timing figure 4.9 shows the timing for transition to the bus-released state. cpu cycle external-bus-released state cpu cycle minimum 1 state t 0 t 1 t 2 address bus hwr lwr breq back breqo as rd breq back breq breq back breqo back figure 4.9 bus-released state transition timing
90 4.7.5 usage note if mstpcr is set to h'ffff or h'efff and a transition is made to sleep mode, the external bus release function will halt. therefore, these settings should not be used. 4.8 bus arbitration 4.8.1 overview the h8s/2319 and h8s/2318 series have a bus arbiter that arbitrates bus master operations. there are two bus masters, the cpu and dtc which perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 4.8.2 operation the bus arbiter monitors the bus masters bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low) an external access by an internal bus master and external bus release can be executed in parallel. if an external bus release request and an external access by an internal bus master occur simultaneously, the order of priority is as follows: (high) external bus release > internal bus master external access (low) 4.8.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus.
91 cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? ? dtc: the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). it does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 4.8.4 note on use of external bus release external bus release can be performed on completion of an external bus cycle. the rd rd 4.9 bus controller operation in a reset in a reset, the chip, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted.
92
93 section 5 i/o ports 5.1 overview the h8s/2319 and h8s/2318 series have 10 i/o ports (ports 1, 2, 3, and a to g), and one input- only port (port 4). table 5.1 summarizes the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only ports), a data register (dr) that stores output data, and a port register (port) used to read the pin states. ports a to e have a built-in mos pull-up function, and in addition to dr and ddr, have a mos input pull-up control register (pcr) to control the on/off state of mos input pull-up. port 3 and port a include an open drain control register (odr) that controls the on/off state of the output buffer pmos. ports 1, a to f can drive a single ttl load and 50 pf capacitive load, and ports 2, 3, and g can drive a single ttl load and 30 pf capacitive load. ports 1, 2, and ports 34, 35 (only when used as irq inputs), ports f0 to f3 (only when used as irq inputs), ports g0 and g1 (only when used as irq inputs) are schmitt-triggered inputs.
94 table 5.1 port functions port description pins mode 4 mode 5 mode 6 * 1 mode 7 * 1 port 1 ? 8-bit i/o port ? schmitt- triggered input p17/tiocb2/tclkd p16/tioca2 p15/tiocb1/tclkc p14/tioca1 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2) p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 when ddr = 0: input port also functioning as tpu i/o pins (tclka, tclkb, tioca0, tiocb0, tiocc0, tiocd0) when ddr = 1 and a23e to a20e = 1: address output when ddr = 1 and a23e to a20e = 0: dr value output port 2 ? 8-bit i/o port ? schmitt- triggered input p27/tiocb5/tmo1 p26/tioca5/tmo0 p25/tiocb4/tmci1 p24/tioca4/tmri1 p23/tiocd3/tmci0 p22/tiocc3/tmri0 p21/tiocb3 p20/tioca3 8-bit i/o port also functioning as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5), and 8-bit timer (channels 0 and 1) i/o pins (tmri0, tmci0, tmo0, tmri1, tmci1, tmo1) port 3 ? 6-bit i/o port ? open-drain output capability ? schmitt- triggered input ( irq5 , irq4 ) p35/sck1/ irq5 p34/sck0/ irq4 p33/rxd1 p32/rxd0 p31/txd1 p30/txd0 6-bit i/o port also functioning as sci (channels 0 and 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1) and interrupt input pins ( irq5 , irq4 )
95 port description pins mode 4 mode 5 mode 6 * 1 mode 7 * 1 port 4 ? 8-bit input port p47/an7/da1 p46/an6/da0 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 8-bit input port also functioning as a/d converter analog inputs (an7 to an0) and d/a converter analog outputs (da1 and da0) port a ? 4-bit i/o port ? built-in mos input pull-up ? open-drain output capability pa3/a19 to pa0/a16 address output when ddr = 0 (after reset): input ports when ddr = 1: address output i/o ports port b ? 8-bit i/o port ? built-in mos input pull-up pb7/a15 to pb0/a8 address output when ddr = 0 (after reset): input port when ddr = 1: address output i/o port port c ? 8-bit i/o port ? built-in mos input pull-up pc7/a7 to pc0/a0 address output when ddr = 0 (after reset): input port when ddr = 1: address output i/o port port d ? 8-bit i/o port ? built-in mos input pull-up pd7/d15 to pd0/d8 data bus input/output i/o port
96 port description pins mode 4 mode 5 mode 6 * 1 mode 7 * 1 port e ? 8-bit i/o port ? built-in mos input pull-up pe7/d7 to pe0/d0 in 8-bit bus mode: i/o port in 16-bit bus mode: data bus input/output i/o port port f ? 8-bit i/o port ? schmitt- triggered input ( irq3 to irq0 ) pf7/ when ddr = 0: input port when ddr = 1 (after reset): ?output when ddr = 0 (after reset): input port when ddr = 1: ?output pf6/ as when asod = 1: i/o port when asod = 0: as output i/o port pf5/ rd pf4/ hwr rd , hwr output pf3/ lwr / irq3 in 8-bit bus mode: when lwrod = 1, i/o port in 16-bit bus mode: lwr output also functioning as interrupt input pin ( irq3 ) i/o port also functioning as interrupt input pins ( irq3 to irq0 ) pf2/ wait / irq2 / breqo when waite = 0, brle = 0, breqoe = 0 (after reset): i/o port also functioning as interrupt input pin ( irq2 ) when waite = 1: wait input also functioning as interrupt input pin ( irq2 ) when waite = 0, brle = 1, breqoe = 1: breqo output also functioning as interrupt input pin ( irq2 ) pf1/ back / irq1 / cs5 pf0/ breq / irq0 / cs4 when brle = 0 (after reset): i/o port also functioning as interrupt input pins ( irq1 , irq0 ) when cs25e = 1, pf1cs5s = 1, and ddr = 1: also functions as cs5 output when cs25e = 1, pf0cs4s = 1, and ddr = 1: also functions as cs4 output when brle = 1: breq input, back output also functioning as interrupt input pins ( irq1 , irq0 )
97 port description pins mode 4 mode 5 mode 6 * 1 mode 7 * 1 port g ? 5-bit i/o port ? schmitt- triggered input ( irq7 , irq6 ) pg4/ cs0 when ddr = 0 * 2 : input port when ddr = 1 * 3 : cs0 output i/o port also functions as interrupt input pins ( irq7 , irq6 ) and a/d converter input pin ( adtrg ) pg3/ cs1 / cs7 i/o port when ddr = 1, cs167e = 1, and css17 = 0: also functions as cs1 output when ddr = 1, cs167e = 1, and css17 = 1: also functions as cs7 output pg2/ cs2 i/o port when ddr = 1 and cs25e = 1: also functions as cs2 output pg1/ cs3 / irq7 / cs6 i/o port when ddr = 1, cs25e = 1, and css36 = 0: also functions as cs3 output when ddr = 1, css36 = 1, and cs167e = 1: also functions as cs6 output and interrupt input pin ( irq7 ) pg0/ irq6 / adtrg i/o port also functioning as interrupt input pin ( irq6 ) and a/d converter input pin ( adtrg ) notes: 1. modes 6 and 7 are not available on the romless version. 2. after a reset in mode 6 3. after a reset in mode 4 or 5
98 5.2 port 1 5.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2) and an address bus output function. port 1 pin functions change according to the operating mode. the address output or port output function is selected according to the settings of bits a23e to a20e in pfcr1. port 1 pins have schmitt-trigger inputs. figure 5.1 shows the port 1 pin configuration. p17 (i/o)/tiocb2 (i/o)/tclkd (input) p16 (i/o)/tioca2 (i/o) p15 (i/o)/tiocb1 (i/o)/tclkc (input) p14 (i/o)/tioca1 (i/o) p13 (i/o)/tiocd0 (i/o)/tclkb (input)/a23 (output) p12 (i/o)/tiocc0 (i/o)/tclka (input)/a22 (output) p11 (i/o)/tiocb0 (i/o)/a21 (output) p10 (i/o)/tioca0 (i/o)/a20 (output) port 1 note: * modes 6 and 7 are not available on the romless version. port 1 pins p17 (i/o)/tiocb2 (i/o)/tclkd (input) p16 (i/o)/tioca2 (i/o) p15 (i/o)/tiocb1 (i/o)/tclkc (input) p14 (i/o)/tioca1 (i/o) p13 (i/o)/tiocd0 (i/o)/tclkb (input) p12 (i/o)/tiocc0 (i/o)/tclka (input) p11 (i/o)/tiocb0 (i/o) p10 (i/o)/tioca0 (i/o) pin functions in mode 7 * p17 (i/o)/tiocb2 (i/o)/tclkd (input) p16 (i/o)/tioca2 (i/o) p15 (i/o)/tiocb1 (i/o)/tclkc (input) p14 (i/o)/tioca1 (i/o) p13 (i/o)/tiocd0 (i/o)/tclkb (input)/a23 (output) p12 (i/o)/tiocc0 (i/o)/tclka (input)/a22 (output) p11 (i/o)/tiocb0 (i/o)/a21 (output) p10 (i/o)/tioca0 (i/o)/a20 (output) pin functions in modes 4 to 6 * figure 5.1 port 1 pin functions
99 5.2.2 register configuration table 5.2 shows the port 1 register configuration. table 5.2 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'feb0 port 1 data register p1dr r/w h'00 h'ff60 port 1 register port1 r undefined h'ff50 port function control register 1 pfcr1 r/w h'0f h'ff45 note: * lower 16 bits of the address. port 1 data direction register (p1ddr) bit :7 65 43 21 0 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr initial value : 0 0 0 0 0 0 0 0 r/w:w ww ww ww w p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. setting a p1ddr bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p1ddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. whether the address output pins maintain their output state or go to the high-impedance state in a transition to software standby mode is selected by the ope bit in sbycr. port 1 data register (p1dr) bit :7 65 43 21 0 p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p17 to p10).
100 p1dr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. port 1 register (port1) bit :7 65 43 21 0 p17 p16 p15 p14 p13 p12 p11 p10 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins p17 to p10. port1 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 1 pins (p17 to p10) must always be performed on p1dr. if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port1 contents are determined by the pin states, as p1ddr and p1dr are initialized. port1 retains its prior state after in software standby mode. port function control register 1 (pfcr1) bit:7 65 43 21 0 css17 css36 pf1cs5s pf0cs4s a23e a22e a21e a20e initial value : 0 0 0 0 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pfcr1 is an 8-bit readable/writable register that performs i/o port control. pfcr1 is initialized to h'0f by a reset, and in hardware standby mode. bit 7?s17 select (css17): selects whether cs1 or cs7 is output from the pg3 pin. for details see section 5.12 port g. bit 6?s36 select (css36): selects whether cs3 or cs6 is output from the pg1 pin. for details, see section 5.12 port g. bit 5?ort f1 chip select 5 select (pf1cs5s): selects enabling or disabling of cs5 output. for details, see section 5.11 port f. bit 4?ort f0 chip select 4 select (pf0cs4s): selects enabling or disabling of cs4 output. for details, see section 5.11 port f.
101 bit 3?ddress 23 enable (a23e): enables or disables address output 23 (a23). this bit is valid in modes 4 to 6. bit 3 a23e description 0 p13dr is output when p13ddr = 1 1 a23 is output when p13ddr = 1 (initial value) bit 2?ddress 22 enable (a22e): enables or disables address output 22 (a22). this bit is valid in modes 4 to 6. bit 2 a22e description 0 p12dr is output when p12ddr = 1 1 a22 is output when p12ddr = 1 (initial value) bit 1?ddress 21 enable (a21e): enables or disables address output 21 (a21). this bit is valid in modes 4 to 6. bit 1 a21e description 0 p11dr is output when p11ddr = 1 1 a21 is output when p11ddr = 1 (initial value) bit 0?ddress 20 enable (a20e): enables or disables address output 20 (a20). this bit is valid in modes 4 to 6. bit 0 a20e description 0 p10dr is output when p10ddr = 1 1 a20 is output when p10ddr = 1 (initial value) 5.2.3 pin functions port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2) and address output pins (a23 to a20). port 1 pin functions are shown in table 5.3.
102 table 5.3 port 1 pin functions pin selection method and pin functions p17/tiocb2/ tclkd the pin function is switched as shown below according to the combination of the tpu channel 2 setting by bits md3 to md0 in tmdr2, bits iob3 to iob0 in tior2, bits cclr1 and cclr0 in tcr2, bits tpsc2 to tpsc0 in tcr0 and tcr5, and bit p17ddr. tpu channel 2 setting table below (1) table below (2) p17ddr 01 pin function tiocb2 output p17 input p17 output tiocb2 input * 1 tclkd input * 2 tpu channel 2 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don t care notes: 1. tiocb2 input when md3 to md0 = b'0000 or b'01xx and iob3 = 1. 2. tclkd input when the setting for either tcr0 or tcr5 is: tpsc2 to tpsc0 = b'111. tclkd input when channels 2 and 4 are set to phase counting mode (md3 to md0 = b'01xx).
103 pin selection method and pin functions p16/tioca2 the pin function is switched as shown below according to the combination of the tpu channel 2 setting by bits md3 to md0 in tmdr2, bits ioa3 to ioa0 in tior2, bits cclr1 and cclr0 in tcr2, and bit p16ddr. tpu channel 2 setting table below (1) table below (2) p16ddr 01 pin function tioca2 output p16 input p16 output tioca2 input * 1 tpu channel 2 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0011 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don t care notes: 1. tioca2 input when md3 to md0 = b'0000 or b'01xx and ioa3 = 1. 2. tiocb2 output is disabled.
104 pin selection method and pin functions p15/tiocb1/ tclkc the pin function is switched as shown below according to the combination of the tpu channel 1 setting by bits md3 to md0 in tmdr1, bits iob3 to iob0 in tior1, bits cclr1 and cclr0 in tcr1, bits tpsc2 to tpsc0 in tcr0, tcr2, tcr4, and tcr5, and bit p15ddr. tpu channel 1 setting table below (1) table below (2) p15ddr 01 pin function tiocb1 output p15 input p15 output tiocb1 input * 1 tclkc input * 2 tpu channel 1 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don t care notes: 1. tiocb1 input when md3 to md0 = b'0000 or b'01xx and iob3 to iob0 = b'10xx. 2. tclkc input when the setting for either tcr0 or tcr2 is: tpsc2 to tpsc0 = b'110; or when the setting for either tcr4 or tcr5 is tpsc2 to tpsc0 = b'101. tclkc input when channels 2 and 4 are set to phase counting mode (md3 to md0 = b'01xx).
105 pin selection method and pin functions p14/tioca1 the pin function is switched as shown below according to the combination of the tpu channel 1 setting by bits md3 to md0 in tmdr1, bits ioa3 to ioa0 in tior1, bits cclr1 and cclr0 in tcr1, and bit p14ddr. tpu channel 1 setting table below (1) table below (2) p14ddr 01 pin function tioca1 output p14 input p14 output tioca1 input * 1 tpu channel 1 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don't care notes: 1. tioca1 input when md3 to md0 = b'0000 or b'01xx and ioa3 to ioa0 = b'10xx. 2. tiocb1 output is disabled.
106 pin selection method and pin functions p13/tiocd0/ tclkb/a23 the pin function is switched as shown below according to the combination of the operating mode, tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr2, bit a23e in pfcr1, and bit p13ddr. operating mode mode 7 * 1 modes 4, 5, 6 * 1 tpu channel 0 setting table below (1) table below (2) table below (1) table below (2) p13ddr 01 0 1 0 1 a23e 01 01 pin function tiocd0 output p13 input p13 output tiocd0 output tiocd0 output a23 output p13 input p13 output a23 output tiocd0 input * 2 tiocd0 input * 2 tclkb input * 3 tpu channel 0 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: don t care notes: 1. modes 6 and 7 are not available on the romless version. 2. tiocd0 input when md3 to md0 = b'0000 and iod3 to iod0 = b'10xx. 3. tclkb input when the tcr0, tcr1, or tcr2 setting is: tpsc2 to tpsc0 = b'101. tclkb input when channels 1 and 5 are set to phase counting mode (md3 to md0 = b'01xx).
107 pin selection method and pin functions p12/tiocc0/ tclka/a22 the pin function is switched as shown below according to the combination of the operating mode, tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr5, bit a22e in pfcr1 and bit p12ddr. operating mode mode 7 * 1 modes 4, 5, 6 * 1 tpu channel 0 setting table below (1) table below (2) table below (1) table below (2) p12ddr 01 0 1 0 1 a22e 01 01 pin function tiocc0 output p12 input p12 output tiocc0 output tiocc0 output a22 output p12 input p12 output a22 output tiocc0 input * 2 tiocc0 input * 2 tclka input * 3 tpu channel 0 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output function output compare output pwm mode 1 output * 4 pwm mode 2 output x: don t care notes: 1. modes 6 and 7 are not available on the romless version. 2. tiocc0 input when md3 to md0 = b'0000 and ioc3 to ioc0 = b'10xx. 3. tclka input when the tcr0 to tcr5 setting is: tpsc2 to tpsc0 = b'100. tclka input when channel 1 and 5 are set to phase counting mode (md3 to md0 = b'01xx). 4. tiocd0 output is disabled. when bfa = 1 or bfb = 1 in tmdr0, output is disabled and setting (2) applies.
108 pin selection method and pin functions p11/tiocb0/ a21 the pin function is switched as shown below according to the combination of the operating mode, tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits iob3 to iob0 in tior0h, and bits cclr2 to cclr0 in tcr0), bit a21e in pfcr1 and bit p11ddr. operating mode mode 7 * 1 modes 4, 5, 6 * 1 tpu channel 0 setting table below (1) table below (2) table below (1) table below (2) p11ddr 01 0 1 0 1 a21e 01 01 pin function tiocb0 output p11 input p11 output tiocb0 output tiocb0 output a21 output p11 input p11 output a21 output tiocb0 input * 2 tiocb0 input * 2 tclkb input * 3 tpu channel 0 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: don t care notes: 1. modes 6 and 7 are not available on the romless version. 2. tiocb0 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx.
109 pin selection method and pin functions p10/tioca0/ a20 the pin function is switched as shown below according to the combination of the operating mode, tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, and bits cclr2 to cclr0 in tcr0), bit a20e in pfcr1 and bit p10ddr. operating mode mode 7 * 1 modes 4, 5, 6 * 1 tpu channel 0 setting table below (1) table below (2) table below (1) table below (2) p10ddr 01 0 1 0 1 a20e 01 01 pin function tioca0 output p10 input p10 output tioca0 output tioca0 output a20 output p10 input p10 output a20 output tioca0 input * 2 tioca0 input * 2 tpu channel 0 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output function output compare output pwm mode 1 output * 3 pwm mode 2 output x: don t care notes: 1. modes 6 and 7 are not available on the romless version. 2. tioca0 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. 3. tiocb0 output is disabled.
110 5.3 port 2 5.3.1 overview port 2 is an 8-bit i/o port. port 2 pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5), and 8-bit timer i/o pins (tmri0, tmci0, tmo0, tmri1, tmci1, and tmo1). port 2 pin functions are the same in all operating modes. port 2 uses schmitt-triggered input. figure 5.2 shows the port 2 pin configuration. p27 (i/o)/tiocb5 (i/o)/tmo1 (output) p26 (i/o)/tioca5 (i/o)/tmo0 (output) p25 (i/o)/tiocb4 (i/o)/tmci1 (input) p24 (i/o)/tioca4 (i/o)/tmri1 (input) p23 (i/o)/tiocd3 (i/o)/tmci0 (input) p22 (i/o)/tiocc3 (i/o)/tmri0 (input) p21 (i/o)/tiocb3 (i/o) p20 (i/o)/tioca3 (i/o) port 2 port 2 pins figure 5.2 port 2 pin functions 5.3.2 register configuration table 5.4 shows the port 2 register configuration. table 5.4 port 2 registers name abbreviation r/w initial value address * port 2 data direction register p2ddr w h'00 h'feb1 port 2 data register p2dr r/w h'00 h'ff61 port 2 register port2 r undefined h'ff51 note: * lower 16 bits of the address.
111 port 2 data direction register (p2ddr) bit :7 65 43 21 0 p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr initial value : 0 0 0 0 0 0 0 0 r/w:w ww ww ww w p2ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. p2ddr cannot be read; if it is, an undefined value will be read. setting a p2ddr bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p2ddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. port 2 data register (p2dr) bit :7 65 43 21 0 p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w p2dr is an 8-bit readable/writable register that stores output data for the port 2 pins (p27 to p20). p2dr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. port 2 register (port2) bit :7 65 43 21 0 p27 p26 p25 p24 p23 p22 p21 p20 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins p27 to p20. port2 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 2 pins (p27 to p20) must always be performed on p2dr. if a port 2 read is performed while p2ddr bits are set to 1, the p2dr values are read. if a port 2 read is performed while p2ddr bits are cleared to 0, the pin states are read.
112 after a reset and in hardware standby mode, port2 contents are determined by the pin states, as p2ddr and p2dr are initialized. port2 retains its prior state after in software standby mode. 5.3.3 pin functions port 2 pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5), and 8-bit timer i/o pins (tmri0, tmci0, tmo0, tmri1, tmci1, and tmo1). port 2 pin functions are shown in table 5.5. table 5.5 port 2 pin functions pin selection method and pin functions p27/tiocb5/ tmo1 the pin function is switched as shown below according to the combination of the tpu channel 5 setting by bits md3 to md0 in tmdr5, bits iob3 to iob0 in tior5, bits cclr1 and cclr0 in tcr5, bits os3 to os0 in tcsr1, and bit p27ddr. os3 to os0 all 0 any 1 tpu channel 5 setting table below (1) table below (2) p27ddr 01 pin function tiocb5 output p27 input p27 output tmo1 output tiocb5 input * tpu channel 5 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don t care note: * tiocb5 input when md3 to md0 = b'0000 or b'01xx and iob3 = 1.
113 pin selection method and pin functions p26/tioca5/ tmo0 the pin function is switched as shown below according to the combination of the tpu channel 5 setting by bits md3 to md0 in tmdr5, bits ioa3 to ioa0 in tior5, bits cclr1 and cclr0 in tcr5, bits os3 to os0 in tcsr0, and bit p26ddr. os3 to os0 all 0 any 1 tpu channel 5 setting table below (1) table below (2) p26ddr 01 pin function tioca5 output p26 input p26 output tmo0 output tioca5 input * 1 tpu channel 5 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don t care notes: 1. tioca5 input when md3 to md0 = b'0000 or b'01xx and ioa3 = 1. 2. tiocb5 output is disabled.
114 pin selection method and pin functions p25/tiocb4/ tmci1 this pin is used as the 8-bit timer external clock input pin when external clock is selected with bits cks2 to cks0 in tcr1. the pin function is switched as shown below according to the combination of the tpu channel 4 setting by bits md3 to md0 in tmdr4 and bits iob3 to iob0 in tior4, bits cclr1 and cclr0 in tcr4, and bit p25ddr. tpu channel 4 setting table below (1) table below (2) p25ddr 01 pin function tiocb4 output p25 input p25 output tiocb4 input * tmci1 input tpu channel 4 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don t care note: * tiocb4 input when md3 to md0 = b'0000 or b'10xx and iob3 to iob0 = b'10xx.
115 pin selection method and pin functions p24/tioca4/ tmri1 this pin is used as the 8-bit timer counter reset pin when bits cclr1 and cclr0 in tcr1 are both set to 1. the pin function is switched as shown below according to the combination of the tpu channel 4 setting by bits md3 to md0 in tmdr4, bits ioa3 to ioa0 in tior4, bits cclr1 and cclr0 in tcr4, and bit p24ddr. tpu channel 4 setting table below (1) table below (2) p24ddr 01 pin function tioca4 output p24 input p24 output tioca4 input * 1 tmri1 input tpu channel 4 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don t care notes: 1. tioca4 input when md3 to md0 = b'0000 or b'01xx and ioa3 to ioa0 = b'10xx. 2. tiocb4 output is disabled.
116 pin selection method and pin functions p23/tiocd3/ tmci0 this pin is used as the 8-bit timer external clock input pin when external clock is selected with bits cks2 to cks0 in tcr0. the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits iod3 to iod0 in tior3l, bits cclr2 to cclr0 in tcr3, and bit p23ddr. tpu channel 3 setting table below (1) table below (2) p23ddr 01 pin function tiocd3 output p23 input p23 output tiocd3 input * tmci0 input tpu channel 3 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: don t care note: * tiocd3 input when md3 to md0 = b'0000 and iod3 to iod0 = b'10xx.
117 pin selection method and pin functions p22/tiocc3/ tmri0 this pin is used as the 8-bit timer counter reset pin when bits cclr1 and cclr0 in tcr0 are both set to 1. the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits ioc3 to ioc0 in tior3l, bits cclr2 to cclr0 in tcr3, and bit p22ddr. tpu channel 3 setting table below (1) table below (2) p22ddr 01 pin function tiocc3 output p22 input p22 output tiocc3 input * 1 tmri0 input tpu channel 3 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don t care notes: 1. tiocc3 input when md3 to md0 = b'0000 and ioc3 to ioc0 = b'10xx. 2. tiocd3 output is disabled. when bfa = 1 or bfb = 1 in tmdr3, output is disabled and setting (2) applies.
118 pin selection method and pin functions p21/tiocb3 the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits iob3 to iob0 in tior3h, bits cclr2 to cclr0 in tcr3, and bit p21ddr. tpu channel 3 setting table below (1) table below (2) p21ddr 01 pin function tiocb3 output p21 input p21 output tiocb3 input * tpu channel 3 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: don t care note: * tiocb3 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx.
119 pin selection method and pin functions p20/tioca3 the pin function is switched as shown below according to the combination of the tpu channel 3 setting by bits md3 to md0 in tmdr3, bits ioa3 to ioa0 in tior3h, bits cclr2 to cclr0 in tcr3, and bit p20ddr. tpu channel 3 setting table below (1) table below (2) p20ddr 01 pin function tioca3 output p20 input p20 output tioca3 input * 1 tpu channel 3 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don t care notes: 1. tioca3 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. 2. tiocb3 output is disabled.
120 5.4 port 3 5.4.1 overview port 3 is a 6-bit i/o port. port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1) and interrupt input pins ( irq4 , irq5 ). port 3 pin functions are the same in all operating modes. the interrupt input pins ( irq4 , irq5 ) are schmitt-triggered inputs. figure 5.3 shows the port 3 pin configuration. p35 p34 p33 p32 p31 p30 (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ sck1 sck0 rxd1 rxd0 txd1 txd0 (i/o)/ (i/o)/ (input) (input) (output) (output) port 3 pins port 3 irq5 (input) irq4 (input) figure 5.3 port 3 pin functions 5.4.2 register configuration table 5.6 shows the port 3 register configuration. table 5.6 port 3 registers name abbreviation r/w initial value * 1 address * 2 port 3 data direction register p3ddr w h'00 h'feb2 port 3 data register p3dr r/w h'00 h'ff62 port 3 register port3 r undefined h'ff52 port 3 open drain control register p3odr r/w h'00 h'ff76 notes: 1. value of bits 5 to 0. 2 . lower 16 bits of the address.
121 port 3 data direction register (p3ddr) bit :7 65 43 21 0 p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr initial value : undefined undefined 0 0 0 0 0 0 r/w : wwwwww p3ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. bits 7 and 6 are reserved. p3ddr cannot be read; if it is, an undefined value will be read. setting a p3ddr bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p3ddr is initialized to h'00 (bits 5 to 0) by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. as the sci is initialized, the pin states are determined by the p3ddr and p3dr specifications. port 3 data register (p3dr) bit :7 65 43 21 0 p35dr p34dr p33dr p32dr p31dr p30dr initial value : undefined undefined 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w p3dr is an 8-bit readable/writable register that stores output data for the port 3 pins (p35 to p30). bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. p3dr is initialized to h'00 (bits 5 to 0) by a on reset, and in hardware standby mode. it retains its prior state after in software standby mode.
122 port 3 register (port3) bit :7 65 43 21 0 p35 p34 p33 p32 p31 p30 initial value : undefined undefined * * * * * * r/w : rrrrrr note: * determined by state of pins p35 to p30. port3 is an 8-bit read-only register that shows the pin states, and cannot be modified. writing of output data for the port 3 pins (p35 to p30) must always be performed on p3dr. bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, port3 contents are determined by the pin states, as p3ddr and p3dr are initialized. port3 retains its prior state after in software standby mode. port 3 open drain control register (p3odr) bit :7 65 43 21 0 p35odr p34odr p33odr p32odr p31odr p30odr initial value : undefined undefined 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w p3odr is an 8-bit readable/writable register that controls the pmos on/off status for each port 3 pin (p35 to p30). bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. setting a p3odr bit to 1 makes the corresponding port 3 pin an nmos open-drain output pin, while clearing the bit to 0 makes the pin a cmos output pin. p3odr is initialized to h'00 (bits 5 to 0) by a reset, and in hardware standby mode. it retains its prior state after in software standby mode.
123 5.4.3 pin functions port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1) and interrupt input pins ( irq4 , irq5 ). port 3 pin functions are shown in table 5.7. table 5.7 port 3 pin functions pin selection method and pin functions p35/sck1/ irq5 the pin function is switched as shown below according to the combination of bit c/ a in the sci1 smr, bits cke0 and cke1 in scr, and bit p35ddr. cke1 0 1 c/ a 01 cke0 0 1 p35ddr 0 1 pin function p35 input pin p35 output pin * 1 sck1 output pin * 1 sck1 output pin * 1 sck1 input pin irq5 interrupt input pin * 2 notes: 1. when p35odr = 1, the pin becomes an nmos open-drain output. 2. when this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. p34/sck0/ irq4 the pin function is switched as shown below according to the combination of bit c/ a in the sci0 smr, bits cke0 and cke1 in scr, and bit p34ddr. cke1 0 1 c/ a 01 cke0 0 1 p34ddr 0 1 pin function p34 input pin p34 output pin * 1 sck0 output pin * 1 sck0 output pin * 1 sck0 input pin irq4 interrupt input pin * 2 notes: 1. when p34odr = 1, the pin becomes an nmos open-drain output. 2. when this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions.
124 pin selection method and pin functions p33/rxd1 the pin function is switched as shown below according to the combination of bit re in the sci1 scr, and bit p33ddr. re 0 1 p33ddr 0 1 pin function p33 input pin p33 output pin * rxd1 input pin note: * when p33odr = 1, the pin becomes an nmos open-drain output. p32/rxd0 the pin function is switched as shown below according to the combination of bit re in the sci0 scr, and bit p32ddr. re 0 1 p32ddr 0 1 pin function p32 input pin p32 output pin * rxd0 input pin note: * when p32odr = 1, the pin becomes an nmos open-drain output. p31/txd1 the pin function is switched as shown below according to the combination of bit te in the sci1 scr, and bit p31ddr. te 0 1 p31ddr 0 1 pin function p31 input pin p31 output pin * txd1 output pin note: * when p31odr = 1, the pin becomes an nmos open-drain output. p30/txd0 the pin function is switched as shown below according to the combination of bit te in the sci0 scr, and bit p30ddr. te 0 1 p30ddr 0 1 pin function p30 input pin p30 output pin * txd0 output pin note: * when p30odr = 1, the pin becomes an nmos open-drain output.
125 5.5 port 4 5.5.1 overview port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1). port 4 pin functions are the same in all operating modes. figure 5.4 shows the port 4 pin configuration. p47 (input) / an7 (input) / da1 (output) p46 (input) / an6 (input) / da0 (output) p45 (input) / an5 (input) p44 (input) / an4 (input) p43 (input) / an3 (input) p42 (input) / an2 (input) p41 (input) / an1 (input) p40 (input) / an0 (input) port 4 pins port 4 figure 5.4 port 4 pin functions 5.5.2 register configuration table 5.8 shows the port 4 register configuration. port 4 is an input-only port, and does not have a data direction register or data register. table 5.8 port 4 register name abbreviation r/w initial value address * port 4 register port4 r undefined h'ff53 note: * lower 16 bits of the address. port 4 register (port4): the pin states are always read when a port 4 read is performed. bit:7 65 43 21 0 p47 p46 p45 p44 p43 p42 p41 p40 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins p47 to p40.
126 5.5.3 pin functions port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1). 5.6 port a 5.6.1 overview port a is a 4-bit i/o port. port a pins also function as address bus outputs. the pin functions change according to the operating mode. port a has a built-in mos input pull-up function that can be controlled by software. figure 5.5 shows the port a pin configuration. pa3/ a19 pa2/ a18 pa1/ a17 pa0/ a16 note: * modes 6 and 7 are not available on the romless version. port a pins a19 (output) a18 (output) a17 (output) a16 (output) pin functions in modes 4 and 5 pa3 (input)/a19 (output) pa2 (input)/a18 (output) pa1 (input)/a17 (output) pa0 (input)/a16 (output) pin functions in mode 6 * pa3 (i/o) pa2 (i/o) pa1 (i/o) pa0 (i/o) pin functions in mode 7 * port a figure 5.5 port a pin functions
127 5.6.2 register configuration table 5.9 shows the port a register configuration. table 5.9 port a registers name abbreviation r/w initial value * 1 address * 2 port a data direction register paddr w h'0 h'feb9 port a data register padr r/w h'0 h'ff69 port a register porta r undefined h'ff59 port a mos pull-up control register papcr r/w h'0 h'ff70 port a open-drain control register paodr r/w h'0 h'ff77 notes: 1. value of bits 3 to 0. 2. lower 16 bits of the address. port a data direction register (paddr) bit 76543210 pa3ddr pa2ddr pa1ddr pa0ddr initial value undefined undefined undefined undefined 0 0 0 0 r/w wwww paddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. bits 7 to 4 are reserved. paddr is initialized to h'0 (bits 3 to 0) by a reset and in hardware standby mode. it retains its prior state after in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 4 and 5 the corresponding port a pins are address outputs irrespective of the value of bits pa3ddr to pa0ddr. ? mode 6* setting a paddr bit to 1 makes the corresponding port a pin an address output while clearing the bit to 0 makes the pin an input port.
128 ? mode 7* setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. note: * modes 6 and 7 are not available on the romless version. port a data register (padr) bit :7 65 43 21 0 pa3dr pa2dr pa1dr pa0dr initial value : undefined undefined undefined undefined 0 0 0 0 r/w : r/w r/w r/w r/w padr is an 8-bit readable/writable register that stores output data for the port a pins (pa3 to pa0). bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. padr is initialized to h'0 (bits 3 to 0) by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. port a register (porta) bit :7 65 43 21 0 pa3 pa2 pa1 pa0 initial value : undefined undefined undefined undefined * * * * r/w : rrrr note: * determined by state of pins pa3 to pa0. porta is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port a pins (pa3 to pa0) must always be performed on padr. bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, porta contents are determined by the pin states, as paddr and padr are initialized. porta retains its prior state after in software standby mode.
129 port a mos pull-up control register (papcr) bit :7 65 43 21 0 pa3pcr pa2pcr pa1pcr pa0pcr initial value : undefined undefined undefined undefined 0 0 0 0 r/w : r/w r/w r/w r/w papcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port a on an individual bit basis. bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. bits 3 to 0 are valid in modes 6 and 7*, and all the bits are invalid in modes 4 and 5. when a paddr bit is cleared to 0 (input port setting), setting the corresponding papcr bit to 1 turns on the mos input pull-up for the corresponding pin. papcr is initialized to h'0 (bits 3 to 0) by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. note: * modes 6 and 7 are not available on the romless version. port a open drain control register (paodr) bit :7 65 43 21 0 pa3odr pa2odr pa1odr pa0odr initial value : undefined undefined undefined undefined 0 0 0 0 r/w : r/w r/w r/w r/w paodr is an 8-bit readable/writable register that controls whether pmos is on or off for each port a pin (pa3 to pa0). bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. all bits are valid in mode 7.* setting a paodr bit to 1 makes the corresponding port a pin an nmos open-drain output, while clearing the bit to 0 makes the pin a cmos output. paodr is initialized to h'0 (bits 3 to 0) by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. note: * modes 6 and 7 are not available on the romless version.
130 5.6.3 pin functions modes 4 and 5: in modes 4 and 5, the lower 4 bits of port a are designated as address outputs automatically. port a pin functions in modes 4 and 5 are shown in figure 5.6. a19 a18 a17 a16 (output) (output) (output) (output) port a figure 5.6 port a pin functions (modes 4 and 5) mode 6*: in mode 6*, port a pins function as address outputs or input ports. input or output can be specified on an individual bit basis. setting a paddr bit to 1 makes the corresponding port a pin an address output, while clearing the bit to 0 makes the pin an input port. port a pin functions in mode 6 are shown in figure 5.7. a19 a18 a17 a16 pa3 pa2 pa1 pa0 (input) (input) (input) (input) (output) (output) (output) (output) port a when paddr = 1 when paddr = 0 figure 5.7 port a pin functions (mode 6) mode 7*: in mode 7*, port a pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. port a pin functions in mode 7 are shown in figure 5.8.
131 pa3 pa2 pa1 pa0 (i/o) (i/o) (i/o) (i/o) port a figure 5.8 port a pin functions (mode 7) note: * modes 6 and 7 are not available on the romless version. 5.6.4 mos input pull-up function port a has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 6 and 7*, and cannot be used in modes 4 and 5. mos input pull-up can be specified as on or off on an individual bit basis. when a paddr bit is cleared to 0, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained after in software standby mode. table 5.10 summarizes the mos input pull-up states. table 5.10 mos input pull-up states (port a) modes reset hardware standby mode software standby mode in other operations 6, 7 * pa3 to pa0 off off on/off on/off 4, 5 pa3 to pa0 off off legend: off: mos input pull-up is always off. on/off: on when paddr = 0 and papcr = 1; otherwise off. note: * modes 6 and 7 are not available on the romless version.
132 5.7 port b 5.7.1 overview port b is an 8-bit i/o port. port b has an address bus output function, and the pin functions change according to the operating mode. port b has a built-in mos input pull-up function that can be controlled by software. figure 5.9 shows the port b pin configuration. pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2 / a10 pb1 / a9 pb0 / a8 pb7 (input) / a15 (output) pb6 (input) / a14 (output) pb5 (input) / a13 (output) pb4 (input) / a12 (output) pb3 (input) / a11 (output) pb2 (input) / a10 (output) pb1 (input) / a9 (output) pb0 (input) / a8 (output) port b pins pin functions in mode 6 * pin functions in mode 7 * a15 (output) a14 (output) a13 (output) a12 (output) a11 (output) a10 (output) a9 (output) a8 (output) pin functions in modes 4 and 5 pb7 (i/o) pb6 (i/o) pb5 (i/o) pb4 (i/o) pb3 (i/o) pb2 (i/o) pb1 (i/o) pb0 (i/o) port b note: * modes 6 and 7 are not available on the romless version. figure 5.9 port b pin functions
133 5.7.2 register configuration table 5.11 shows the port b register configuration. table 5.11 port b registers name abbreviation r/w initial value address * port b data direction register pbddr w h'00 h'feba port b data register pbdr r/w h'00 h'ff6a port b register portb r undefined h'ff5a port b mos pull-up control register pbpcr r/w h'00 h'ff71 note: * lower 16 bits of the address. port b data direction register (pbddr) bit:7 65 43 21 0 pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr initial value : 0 0 0 0 0 0 0 0 r/w:w ww ww ww w pbddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port b. pbddr cannot be read; if it is, an undefined value will be read. pbddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 4 and 5 the corresponding port b pins are address outputs irrespective of the value of the pbddr bits. ? mode 6* setting a pbddr bit to 1 makes the corresponding port b pin an address output, while clearing the bit to 0 makes the pin an input port. ? mode 7* setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. note: * modes 6 and 7 are not available on the romless version.
134 port b data register (pbdr) bit:7 65 43 21 0 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbdr is an 8-bit readable/writable register that stores output data for the port b pins (pb7 to pb0). pbdr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port b register (portb) bit:7 65 43 21 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins pb7 to pb0. portb is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port b pins (pb7 to pb0) must always be performed on pbdr. if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portb contents are determined by the pin states, as pbddr and pbdr are initialized. portb retains its prior state in software standby mode.
135 port b mos pull-up control register (pbpcr) bit:7 65 43 21 0 pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port b on an individual bit basis. when a pbddr bit is cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pbpcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. 5.7.3 pin functions modes 4 and 5: in modes 4 and 5, port b pins are automatically designated as address outputs. port b pin functions in modes 4 and 5 are shown in figure 5.10. a15 (output) a14 (output) a13 (output) a12 (output) a11 (output) a10 (output) a9 (output) a8 (output) port b figure 5.10 port b pin functions (modes 4 and 5)
136 mode 6*: in mode 6, port b pins function as address outputs or input ports. input or output can be specified on an individual bit basis. setting a pbddr bit to 1 makes the corresponding port b pin an address output, while clearing the bit to 0 makes the pin an input port. port b pin functions in mode 6 are shown in figure 5.11 a15 (output) a14 (output) a13 (output) a12 (output) a11 (output) a10 (output) a9 (output) a8 (output) pb7 (input) pb6 (input) pb5 (input) pb4 (input) pb3 (input) pb2 (input) pb1 (input) pb0 (input) when pbddr = 1 when pbddr = 0 port b figure 5.11 port b pin functions (mode 6) mode 7*: in mode 7, port b pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. port b pin functions in mode 7 are shown in figure 5.12. pb7 (i/o) pb6 (i/o) pb5 (i/o) pb4 (i/o) pb3 (i/o) pb2 (i/o) pb1 (i/o) pb0 (i/o) port b figure 5.12 port b pin functions (mode 7) note: * modes 6 and 7 are not available on the romless version.
137 5.7.4 mos input pull-up function port b has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. when a pbddr bit is cleared to 0 in mode 6 or 7, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 5.12 summarizes the mos input pull-up states. table 5.12 mos input pull-up states (port b) modes reset hardware standby mode software standby mode in other operations 4, 5 off off off off 6, 7 on/off on/off legend off: mos input pull-up is always off. on/off: on when pbddr = 0 and pbpcr = 1; otherwise off.
138 5.8 port c 5.8.1 overview port c is an 8-bit i/o port. port c has an address bus output function, and the pin functions change according to the operating mode. port c has a built-in mos input pull-up function that can be controlled by software. figure 5.13 shows the port c pin configuration. pc7 / a7 pc6 / a6 pc5 / a5 pc4 / a4 pc3 / a3 pc2 / a2 pc1 / a1 pc0 / a0 port c pc7 (input) / a7 (output) pc6 (input) / a6 (output) pc5 (input) / a5 (output) pc4 (input) / a4 (output) pc3 (input) / a3 (output) pc2 (input) / a2 (output) pc1 (input) / a1 (output) pc0 (input) / a0 (output) port c pins pin functions in mode 6 * pin functions in mode 7 * a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) pin functions in modes 4 and 5 pc7 (i/o) pc6 (i/o) pc5 (i/o) pc4 (i/o) pc3 (i/o) pc2 (i/o) pc1 (i/o) pc0 (i/o) note: * modes 6 and 7 are not available on the romless version. figure 5.13 port c pin functions
139 5.8.2 register configuration table 5.13 shows the port c register configuration. table 5.13 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'febb port c data register pcdr r/w h'00 h'ff6b port c register portc r undefined h'ff5b port c mos pull-up control register pcpcr r/w h'00 h'ff72 note: * lower 16 bits of the address. port c data direction register (pcddr) bit:7 65 43 21 0 pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr initial value : 0 0 0 0 0 0 0 0 r/w:w ww ww ww w pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be read. pcddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. ? modes 4 and 5 the corresponding port c pins are address outputs irrespective of the value of the pcddr bits. ? mode 6* setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. ? mode 7* setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. note: * modes 6 and 7 are not available on the romless version.
140 port c data register (pcdr) bit:7 65 43 21 0 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcdr is an 8-bit readable/writable register that stores output data for the port c pins (pc7 to pc0). pcdr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port c register (portc) bit:7 65 43 21 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins pc7 to pc0. portc is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port c pins (pc7 to pc0) must always be performed on pcdr. if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portc contents are determined by the pin states, as pcddr and pcdr are initialized. portc retains its prior state in software standby mode.
141 port c mos pull-up control register (pcpcr) bit:7 65 43 21 0 pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port c on an individual bit basis. when a pcddr bit is cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pcpcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. 5.8.3 pin functions modes 4 and 5: in modes 4 and 5, port c pins are automatically designated as address outputs. port c pin functions in modes 4 and 5 are shown in figure 5.14. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) port c figure 5.14 port c pin functions (modes 4 and 5)
142 mode 6*: in mode 6, port c pins function as address outputs or input ports. input or output can be specified on an individual bit basis. setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. port c pin functions in mode 6 are shown in figure 5.15. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) port c pc7 (input) pc6 (input) pc5 (input) pc4 (input) pc3 (input) pc2 (input) pc1 (input) pc0 (input) when pcddr = 1 when pcddr = 0 figure 5.15 port c pin functions (mode 6) mode 7*: in mode 7, port c pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. port c pin functions in mode 7 are shown in figure 5.16. pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port c (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 5.16 port c pin functions (mode 7) note: * modes 6 and 7 are not available on the romless version.
143 5.8.4 mos input pull-up function port c has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. when a pcddr bit is cleared to 0 in mode 6 or 7, setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 5.14 summarizes the mos input pull-up states. table 5.14 mos input pull-up states (port c) modes reset hardware standby mode software standby mode in other operations 4, 5 off off off off 6, 7 on/off on/off legend off: mos input pull-up is always off. on/off: on when pcddr = 0 and pcpcr = 1; otherwise off.
144 5.9 port d 5.9.1 overview port d is an 8-bit i/o port. port d has a data bus i/o function, and the pin functions change according to the operating mode. port d has a built-in mos input pull-up function that can be controlled by software. figure 5.17 shows the port d pin configuration. pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1 / d9 pd0 / d8 port d d15 (i/o) d14 (i/o) d13 (i/o) d12 (i/o) d11 (i/o) d10 (i/o) d9 (i/o) d8 (i/o) port d pins pin functions in modes 4 to 6 * pd7 (i/o) pd6 (i/o) pd5 (i/o) pd4 (i/o) pd3 (i/o) pd2 (i/o) pd1 (i/o) pd0 (i/o) pin functions in mode 7 * note: * modes 6 and 7 are not available on the romless version. figure 5.17 port d pin functions
145 5.9.2 register configuration table 5.15 shows the port d register configuration. table 5.15 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'febc port d data register pddr r/w h'00 h'ff6c port d register portd r undefined h'ff5c port d mos pull-up control register pdpcr r/w h'00 h'ff73 note: * lower 16 bits of the address. port d data direction register (pdddr) bit:7 65 43 21 0 pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr initial value : 0 0 0 0 0 0 0 0 r/w:w ww ww ww w pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be read. pdddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. ? modes 4 to 6* the input/output direction specification by pdddr is ignored, and port d is automatically designated for data i/o. ? mode 7* setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. note: * modes 6 and 7 are not available on the romless version.
146 port d data register (pddr) bit:7 65 43 21 0 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pddr is an 8-bit readable/writable register that stores output data for the port d pins (pd7 to pd0). pddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port d register (portd) bit:7 65 43 21 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins pd7 to pd0. portd is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port d pins (pd7 to pd0) must always be performed on pddr. if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portd contents are determined by the pin states, as pdddr and pddr are initialized. portd retains its prior state in software standby mode.
147 port d mos pull-up control register (pdpcr) bit:7 65 43 21 0 pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pdpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port d on an individual bit basis. when a pdddr bit is cleared to 0 (input port setting) in mode 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pdpcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. 5.9.3 pin functions modes 4 to 6*: in modes 4 to 6, port d pins are automatically designated as data i/o pins. port d pin functions in modes 4 to 6 are shown in figure 5.18. d15 (i/o) d14 (i/o) d13 (i/o) d12 (i/o) d11 (i/o) d10 (i/o) d9 (i/o) d8 (i/o) port d figure 5.18 port d pin functions (modes 4 to 6)
148 mode 7*: in mode 7, port d pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. port d pin functions in mode 7 are shown in figure 5.19. pd7 (i/o) pd6 (i/o) pd5 (i/o) pd4 (i/o) pd3 (i/o) pd2 (i/o) pd1 (i/o) pd0 (i/o) port d figure 5.19 port d pin functions (mode 7) note: * modes 6 and 7 are not available on the romless version. 5.9.4 mos input pull-up function port d has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. when a pdddr bit is cleared to 0 in mode 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 5.16 summarizes the mos input pull-up states.
149 table 5.16 mos input pull-up states (port d) modes reset hardware standby mode software standby mode in other operations 4 to 6 off off off off 7 on/off on/off legend off: mos input pull-up is always off. on/off: on when pdddr = 0 and pdpcr = 1; otherwise off.
150 5.10 port e 5.10.1 overview port e is an 8-bit i/o port. port e has a data bus i/o function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. port e has a built-in mos input pull-up function that can be controlled by software. figure 5.20 shows the port e pin configuration. pe7 / d7 pe6 / d6 pe5 / d5 pe4 / d4 pe3 / d3 pe2 / d2 pe1 / d1 pe0 / d0 pe7 (i/o) / d7 (i/o) pe6 (i/o) / d6 (i/o) pe5 (i/o) / d5 (i/o) pe4 (i/o) / d4 (i/o) pe3 (i/o) / d3 (i/o) pe2 (i/o) / d2 (i/o) pe1 (i/o) / d1 (i/o) pe0 (i/o) / d0 (i/o) port e pins pin functions in modes 4 to 6 * pin functions in mode 7 * pe7 (i/o) pe6 (i/o) pe5 (i/o) pe4 (i/o) pe3 (i/o) pe2 (i/o) pe1 (i/o) pe0 (i/o) port e note: * modes 6 and 7 are not available on the romless version. figure 5.20 port e pin functions
151 5.10.2 register configuration table 5.17 shows the port e register configuration. table 5.17 port e registers name abbreviation r/w initial value address * port e data direction register peddr w h'00 h'febd port e data register pedr r/w h'00 h'ff6d port e register porte r undefined h'ff5d port e mos pull-up control register pepcr r/w h'00 h'ff74 note: * lower 16 bits of the address. port e data direction register (peddr) bit:7 65 43 21 0 pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr initial value : 0 0 0 0 0 0 0 0 r/w:w ww ww ww w peddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port e. peddr cannot be read; if it is, an undefined value will be read. peddr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. ? modes 4 to 6* when 8-bit bus mode has been selected, port e pins function as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode has been selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. for details of 8-bit and 16-bit bus modes, see section 4, bus controller. ? mode 7* setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. note: * modes 6 and 7 are not available on the romless version.
152 port e data register (pedr) bit:7 65 43 21 0 pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pedr is an 8-bit readable/writable register that stores output data for the port e pins (pe7 to pe0). pedr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. port e register (porte) bit:7 65 43 21 0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins pe7 to pe0. porte is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port e pins (pe7 to pe0) must always be performed on pedr. if a port e read is performed while peddr bits are set to 1, the pedr values are read. if a port e read is performed while peddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, porte contents are determined by the pin states, as peddr and pedr are initialized. porte retains its prior state in software standby mode.
153 port e mos pull-up control register (pepcr) bit:7 65 43 21 0 pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pepcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port e on an individual bit basis. when a peddr bit is cleared to 0 (input port setting) in mode 4, 5, or 6 with 8-bit bus mode selected, or in mode 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for the corresponding pin. pepcr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state in software standby mode. 5.10.3 pin functions modes 4 to 6*: in modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected, port e pins are automatically designated as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. port e pin functions in modes 4 to 6 are shown in figure 5.21. pe7 (i/o) pe6 (i/o) pe5 (i/o) pe4 (i/o) pe3 (i/o) pe2 (i/o) pe1 (i/o) pe0 (i/o) port e d7 (i/o) d6 (i/o) d5 (i/o) d4 (i/o) d3 (i/o) d2 (i/o) d1 (i/o) d0 (i/o) 8-bit bus mode 16-bit bus mode figure 5.21 port e pin functions (modes 4 to 6)
154 mode 7*: in mode 7, port e pins function as i/o ports. input or output can be specified for each pin on a bit-by-bit basis. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. port e pin functions in mode 7 are shown in figure 5.22. pe7 (i/o) pe6 (i/o) pe5 (i/o) pe4 (i/o) pe3 (i/o) pe2 (i/o) pe1 (i/o) pe0 (i/o) port e figure 5.22 port e pin functions (mode 7) note: * modes 6 and 7 are not available on the romless version. 5.10.4 mos input pull-up function port e has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 4, 5, and 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. when a peddr bit is cleared to 0 in mode 4, 5, or 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset, and in hardware standby mode. the prior state is retained in software standby mode. table 5.18 summarizes the mos input pull-up states.
155 table 5.18 mos input pull-up states (port e) modes reset hardware standby mode software standby mode in other operations 7 off off on/off on/off 4 to 6 8-bit bus 16-bit bus off off legend off: mos input pull-up is always off. on/off: on when peddr = 0 and pepcr = 1; otherwise off.
156 5.11 port f 5.11.1 overview port f is an 8-bit i/o port. port f pins also function as bus control signal input/output pins ( as , rd , hwr , lwr , wait , breq , back , breqo , cs4 , and cs5 ), the system clock (? output pin and interrupt input pins ( irq0 to irq3 ). the interrupt input pins ( irq0 to irq3 ) are schmitt-triggered inputs. figure 5.23 shows the port f pin configuration. pf7/ pf6/ as pf5/ rd pf4/ hwr pf3/ lwr / irq3 pf2/ wait / irq2 / breqo pf1/ back / irq1 / cs5 pf0/ breq / irq0 / cs4 port f note: * modes 6 and 7 are not available on the romless version. pf7 (input)/ (output) pf6 (i/o)/ as (output) rd (output) hwr (output) pf3 (i/o)/ lwr (output)/ irq3 (input) pf2 (i/o)/ wait (input)/ irq2 (input)/ breqo (output) pf1 (i/o)/ back (output)/ irq1 (input)/ cs5 (output) pf0 (i/o)/ breq (input)/ irq0 (input)/ cs4 (output) port f pins pin functions in modes 4 to 6 * pf7 (input)/ (output) pf6 (i/o) pf5 (i/o) pf4 (i/o) pf3 (i/o)/ irq3 (input) pf2 (i/o)/ irq2 (input) pf1 (i/o)/ irq1 (input) pf0 (i/o)/ irq0 (input) pin functions in mode 7 * figure 5.23 port f pin functions
157 5.11.2 register configuration table 5.19 shows the port f register configuration. table 5.19 port f registers name abbreviation r/w initial value address * 1 port f data direction register pfddr w h'80/h'00 * 2 h'febe port f data register pfdr r/w h'00 h'ff6e port f register portf r undefined h'ff5e bus control register l bcrl r/w h'3c h'fed5 system control register syscr r/w h'01 h'ff39 port function control register 1 pfcr1 r/w h'0f h'ff45 port function control register 2 pfcr2 r/w h'30 h'ffac notes: 1. lower 16 bits of the address. 2. initial value depends on the mode. port f data direction register (pfddr) bit :7 65 43 21 0 pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr modes 4 to 6 * initial value : 1 0 0 0 0 0 0 0 r/w:w ww ww ww w mode 7 * initial value : 0 0 0 0 0 0 0 0 r/w:w ww ww ww w pfddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port f. pfddr cannot be read; if it is, an undefined value will be read. pfddr is initialized by a reset, and in hardware standby mode, to h'80 in modes 4 to 6*, and to h'00 in mode 7*. it retains its prior state after in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high- impedance when a transition is made to software standby mode. note: * modes 6 and 7 are not available on the romless version.
158 port f data register (pfdr) bit :7 65 43 21 0 pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pfdr is an 8-bit readable/writable register that stores output data for the port f pins (pf7 to pf0). pfdr is initialized to h'00 by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. port f register (portf) bit :7 65 43 21 0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 initial value : * * * * * * * * r/w:r rr rr rr r note: * determined by state of pins pf7 to pf0. portf is an 8-bit read-only register that shows the pin states, and cannot be modified. writing of output data for the port f pins (pf7 to pf0) must always be performed on pfdr. if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portf contents are determined by the pin states, as pfddr and pfdr are initialized. portf retains its prior state after in software standby mode. port function control register 1 (pfcr1) bit:7 65 43 21 0 css17 css36 pf1cs5s pf0cs4s a23e a22e a21e a20e initial value : 0 0 0 0 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pfcr1 is an 8-bit readable/writable register that performs i/o port control. pfcr1 is initialized to h'0f by a reset, and in hardware standby mode. bit 7 cs17 select (css17): selects whether cs1 cs7
159 bit 6 cs36 select (css36): selects whether cs3 cs6 port f1 chip select 5 select (pf1cs5s): selects enabling or disabling of cs5 bit 5 pf1cs5s description 0 pf1 is the pf1/ back / irq1 pin (initial value) 1 pf1 is the pf1/ back / irq1 / cs5 pin. cs5 output is enabled when brle = 0, cs25e = 1, and pf1ddr = 1 bit 4 port f0 chip select 4 select (pf0cs4s): selects enabling or disabling of cs4 bit 4 pf0cs4s description 0 pf0 is the pf0/ breq / irq0 pin (initial value) 1 pf0 is the pf0/ breq / irq0 / cs4 pin. cs4 output is enabled when brle = 0, cs25e = 1, and pf0ddr = 1 bit 3 address 23 enable (a23e): enables or disables address output 23 (a23). for details, see section 5.2 port 1. bit 2 address 22 enable (a22e): enables or disables address output 22 (a22). for details, see section 5.2 port 1. bit 1 address 21 enable (a21e): enables or disables address output 21 (a21). for details, see section 5.2 port 1. bit 0 address 20 enable (a20e): enables or disables address output 20 (a20). for details, see section 5.2 port 1. port function control register 2 (pfcr2) bit:7 65 43 21 0 cs167e cs25e asod initial value : 0 0 1 1 0 0 0 0 r/w : r/w r/w r/w r/w r/w r r r pfcr2 is an 8-bit readable/writable register that performs i/o port control. pfcr2 is initialized to h'30 by a reset, and in hardware standby mode.
160 bits 7 and 6 reserved. bit 5 cs167 enable (cs167e): enables or disables cs1 cs6 cs7 cs25 enable (cs25e): enables or disables cs2 cs3 cs4 cs5 bit 4 cs25e description 0 cs2 , cs3 , cs4 , and cs5 output disabled (can be used as i/o ports) 1 cs2 , cs3 , cs4 , and cs5 output enabled (initial value) bit 3 as output disable (asod): enables or disables as bit 3 asod description 0 pf6 is used as as output pin (initial value) 1 pf6 is designated as i/o port, and does not function as as output pin bits 2 to 0 reserved. system control register (syscr) bit:7 65 43 21 0 intm1 intm0 nmieg lwrod rame initial value : 0 0 0 0 0 0 0 1 r/w : r/w r/w r/w r/w r/w r/w r/w bit 2 lwr output disable (lwrod): enables or disables lwr bit 2 lwrod description 0 pf3 is designated as lwr output pin (initial value) 1 pf3 is designated as i/o port, and does not function as lwr output pin
161 bus control register l (bcrl) bit:7 65 43 21 0 brle breqoe eae waite initial value : 0 0 1 1 1 1 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bcrl is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, selection of the area partition unit, and enabling or disabling of wait bus release enable (brle): enables or disables external bus release. bit 7 brle description 0 external bus release disabled. breq , back , and breqo pins can be used as i/o ports (initial value) 1 external bus release enabled bit 6 breqo pin enable (breqoe): outputs a signal that requests the external bus master to drop the bus request signal ( breq bit 6 breqoe description 0 breqo output disabled. breqo pin can be used as i/o port (initial value) 1 breqo output enabled bit 0 wait pin enable (waite): selects enabling or disabling of wait input by the wait bit 0 waite description 0 wait input by wait pin disabled. wait pin can be used as i/o port (initial value) 1 wait input by wait pin enabled
162 5.11.3 pin functions port f pins also function as bus control signal input/output pins ( as rd hwr lwr wait breq back breqo cs4 cs5 ) output pin and interrupt input pins ( irq0 irq3 pin selection method and pin functions pf7/ the pin function is switched as shown below according to bit pf7ddr. pf7ddr 0 1 pin function pf7 input pin output pin pf6/ as the pin function is switched as shown below according to the operating mode, and bit pf6ddr, and bit asod in pfcr2. operating mode modes 4, 5, 6 * 1 mode 7 * 1 asod 0 1 pf6ddr 0101 pin function as output pin pf6 input pin pf6 output pin pf6 input pin pf6 output pin pf5/ rd the pin function is switched as shown below according to the operating mode and bit pf5ddr. operating mode modes 4, 5, 6 * 1 mode 7 * 1 pf5ddr 01 pin function rd output pin pf5 input pin pf5 output pin pf4/ hwr the pin function is switched as shown below according to the operating mode and bit pf4ddr. operating mode modes 4, 5, 6 * 1 mode 7 * 1 pf4ddr 01 pin function hwr output pin pf4 input pin pf4 output pin
163 pin selection method and pin functions pf3/ lwr / irq3 the pin function is switched as shown below according to the operating mode, and bit pf3ddr, and bit lwrod in syscr. operating mode modes 4, 5, 6 * 1 mode 7 * 1 lwrod 0 1 * 3 pf3ddr 0101 pin function lwr output pin pf3 input pin pf3 output pin pf3 input pin pf3 output pin irq3 interrupt input pin * 2 pf2/ wait / irq2 / breqo the pin function is switched as shown below according to the operating mode, and waite bit, breqoe bit in bcrl and pf2ddr bit. operating mode modes 4, 5, 6 * 1 mode 7 * 1 breqoe 0 1 waite 0 1 0 1 pf2ddr 0 1 0 1 01 pin function pf2 input pin pf2 output pin wait input pin setting prohi- bited breqo output pin setting prohi- bited pf2 input pin pf2 output pin irq2 interrupt input pin * 2
164 pin selection method and pin functions pf1/ back / irq1 / cs5 the pin function is switched as shown below according to the operating mode, and the brle bit in bcrl, pf1cs5s bit in pfcr1, and cs25e bit in pfcr2 and pf1ddr bit. operating mode modes 4, 5, 6 * 1 mode 7 * 1 brle 0 1 pf1ddr 0 1 01 cs25e 01 pf1cs5s 01 pin function pf1 input pin pf1 output pin cs5 output pin back output pin pf1 input pin pf1 output pin irq1 interrupt input pin * 2 pf0/ breq / irq0 / cs4 the pin function is switched as shown below according to the operating mode, and the brle bit in bcrl and pf0cs4s bit in pfcr1 and cs25e bit in pfcr2 and pf0ddr bit. operating mode modes 4, 5, 6 * 1 mode 7 * 1 brle 0 1 pf0ddr 0 1 01 cs25e 01 pf0cs4s 01 pin function pf0 input pin pf0 output pin cs4 output pin breq output pin pf0 input pin pf0 output pin irq0 interrupt input pin * 2 notes: 1. modes 6 and 7 are not available on the romless version. 2. when this pin is used as an external interrupt input, the pin function should be set as a port (pfn) input pin. 3. valid only in 8-bit-bus mode.
165 5.12 port g 5.12.1 overview port g is a 5-bit i/o port. port g pins also function as bus control signal output pins ( cs0 cs3 cs6 cs7 adtrg irq6 irq7 irq6 irq7 pg4/ cs0 pg3/ cs1 / cs7 pg2/ cs2 pg1/ cs3 / irq7 / cs6 pg0/ adtrg / irq6 pg4 pg3 pg2 pg1 pg0 note: * modes 6 and 7 are not available on the romless version. (i/o) (i/o) (i/o) (i/o)/ irq7 (input) (i/o)/ port g pins pin functions in mode 7 * pin functions in modes 4 to 6 * pg4 pg3 pg2 pg1 pg0 (i/o)/ (i/o)/ (i/o)/ (i/o)/ (i/o)/ cs0 cs1 cs2 cs3 (output) (output)/ (output) (output)/ irq7 (input)/ cs7 (output) cs6 (output) port g adtrg (input)/ irq6 (input) adtrg (input)/ irq6 (input) figure 5.24 port g pin functions
166 5.12.2 register configuration table 5.21 shows the port g register configuration. table 5.21 port g registers name abbreviation r/w initial value * 1 address * 2 port g data direction register pgddr w h'10/h'00 * 3 h'febf port g data register pgdr r/w h'00 h'ff6f port g register portg r undefined h'ff5f port function control register 1 pfcr1 r/w h'0f h'ff45 port function control register 2 pfcr2 r/w h'30 h'ffac notes: 1. value of bits 4 to 0. 2. lower 16 bits of the address. 3. initial value depends on the mode. port g data direction register (pgddr) bit :7 65 43 21 0 pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr modes 4 and 5 initial value : undefined undefined undefined 1 0 0 0 0 r/w : ww ww w modes 6 and 7 * initial value : undefined undefined undefined 0 0 0 0 0 r/w : ww ww w pgddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port g. pgddr cannot be read, and bits 7 to 5 are reserved. if pgddr is read, an undefined value will be read. the pgddr is initialized by a reset and in hardware standby mode, to h'10 (bits 4 to 0) in modes 4 and 5, and to h'00 (bits 4 to 0) in modes 6 and 7*. it retains its prior state after in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. note: * modes 6 and 7 are not available on the romless version.
167 port g data register (pgdr) bit :7 65 43 21 0 pg4dr pg3dr pg2dr pg1dr pg0dr initial value : undefined undefined undefined 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w pgdr is an 8-bit readable/writable register that stores output data for the port g pins (pg4 to pg0). bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. pgdr is initialized to h'00 (bits 4 to 0) by a reset, and in hardware standby mode. it retains its prior state after in software standby mode. port g register (portg) bit :7 65 43 21 0 pg4 pg3 pg2 pg1 pg0 initial value : undefined undefined undefined * * * * * r/w : rr rr r note: * determined by state of pins pg4 to pg0. portg is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port g pins (pg4 to pg0) must always be performed on pgdr. bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. if a port g read is performed while pgddr bits are set to 1, the pgdr values are read. if a port g read is performed while pgddr bits are cleared to 0, the pin states are read. after a reset and in hardware standby mode, portg contents are determined by the pin states, as pgddr and pgdr are initialized. portg retains its prior state after in software standby mode.
168 port function control register 1 (pfcr1) bit:7 65 43 21 0 css17 css36 pf1cs5s pf0cs4s a23e a22e a21e a20e initial value : 0 0 0 0 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pfcr1 is an 8-bit readable/writable register that performs i/o port control. pfcr1 is initialized to h'0f by a reset, and in hardware standby mode. bit 7 cs17 select (css17): selects whether cs1 cs7 bit 7 css17 description 0 pg3 is the pg3/ cs1 pin. cs1 output is enabled when cs167e = 1 and pg3ddr = 1 (initial value) 1 pg3 is the pg3/ cs7 pin. cs7 output is enabled when cs167e = 1 and pg3ddr = 1 bit 6 cs36 select (css36): selects whether cs3 cs6 bit 6 css36 description 0 pg1 is the pg1/ irq7 / cs3 pin. cs3 output is enabled when cs25e = 1 and pg1ddr = 1 (initial value) 1 pg1 is the pg1/ irq7 / cs6 pin. cs6 output is enabled when cs167e = 1 and pg1ddr = 1 bit 5 port f1 chip select 5 select (pf1cs5s): enables or disables cs5 port f0 chip select 4 select (pf0cs4s): enables or disables cs4 address 23 enable (a23e): enables or disables address output 23 (a23). for details, see section 5.2, port 1. bit 2 address 22 enable (a22e): enables or disables address output 22 (a22). for details, see section 5.2,, port 1.
169 bit 1 address 21 enable (a21e): enables or disables address output 21 (a21). for details, see section 5.2, port 1. bit 0 address 20 enable (a20e): enables or disables address output 20 (a20). for details, see section 5.2, port 1. port function control register 2 (pfcr2) bit:7 65 43 21 0 cs167e cs25e asod initial value : 0 0 1 1 0 0 0 0 r/w : r/w r/w r/w r/w r/w r r r pfcr2 is an 8-bit readable/writable register that performs i/o port control. pfcr2 is initialized to h'30 by a reset, and in hardware standby mode. this bit is valid in modes 4 to 6. bits 7 and 6 reserved. bit 5 cs167 enable (cs167e): enables or disables cs1 cs6 cs7 bit 5 cs167e description 0 cs1 , cs6 , and cs7 output disabled (can be used as i/o ports) 1 cs1 , cs6 , and cs7 output enabled (initial value) bit 4 cs25 enable (cs25e): enables or disables cs2 cs3 cs4 cs5 bit 4 cs25e description 0 cs2 , cs3 , cs4 , and cs5 output disabled (can be used as i/o ports) 1 cs2 , cs3 , cs4 , and cs5 output enabled (initial value) bit 3 as output disable (asod): enables or disables as reserved.
170 5.12.3 pin functions port g pins also function as bus control signal output pins ( cs0 cs3 cs6 cs7 adtrg irq6 irq7 pin selection method and pin functions pg4/ cs0 the pin function is switched as shown below according to the operating mode and bit pg4ddr. operating mode modes 4, 5, 6 * 1 mode 7 * 1 pg4ddr 0 1 0 1 pin function pg4 input pin cs0 output pin pg4 input pin pg4 output pin pg3/ cs1 / cs7 the pin function is switched as shown below according to the operating mode and css17 bit in pfcr1, cs167e bit in pfcr2, and bit pg3ddr. operating mode modes 4, 5, 6 * 1 mode 7 * 1 pg3ddr 0 1 0 1 cs167e 01 css17 01 pin function pg3 input pin pg3 output pin cs1 output pin cs7 output pin pg3 input pin pg3 output pin pg2/ cs2 the pin function is switched as shown below according to the operating mode and cs25e bit in pfcr2, and bit pg2ddr. operating mode modes 4, 5, 6 * 1 mode 7 * 1 pg2ddr 0 1 0 1 cs25e 01 pin function pg2 input pin pg2 output pin cs2 output pin pg2 input pin pg2 output pin
171 pin selection method and pin functions pg1/ cs3 / cs6 / irq7 the pin function is switched as shown below according to the combination of operating mode and css36 bit in pfcr1, cs167e bit in pfcr2, cs25e bit and bit pg1ddr. operating mode modes 4, 5, 6 * 1 mode 7 * 1 pg1ddr 0 1 0 1 cs167e 01 cs25e 0101 css36 010101 pin function pg1 input pin pg1 output pin cs3 output pin pg1 output pin cs6 output pin cs3 output pin cs6 output pin pg1 input pin pg1 output pin irq7 interrupt input pin * 2 pg0/ adtrg / irq6 the pin function is switched as shown below according to the combination of bits trgs1 and trgs0 (trigger select 1 and 0) in the a/d control register (adcr). pg0ddr 0 1 pin function pg0 input pg0 output adtrg input pin * 3 irq6 interrupt input pin * 2 notes: 1. modes 6 and 7 are not available on the romless version. 2. when this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. 3. adtrg input when trgs1 = trgs0 = 1.
172 5.13 pin states 5.13.1 port states in each mode table 5.23 i/o port states in each processing state port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode p17/tiocb2/ tclkd p16/tioca2 p15/tiocb1/ tclkc p14/tioca1 4 to 7 t t kept kept i/o port p13/tiogd0/ tclkb/a23 p12/tiocc0/t clka/a22 p11/tiocb0/ a21 p10/tioca0/ a20 4 to 6 t t [ane = 0] kept [ane ddr = 1] kept [ane ddr ope = 1] t [ane ddr ope = 1] kept [ane = 0] kept [ane ddr = 1] kept [ane ddr = 1] t [ane = 0] i/o port [ane ddr = 1] i/o port [ane ddr = 1] address output 7 t t kept kept i/o port port 2 4 to 7 t t kept kept i/o port port 3 4 to 7 t t kept kept i/o port p47/da1 4 to 7 t t [daoe1 = 1] kept [daoe1 = 0] t kept i/o port p46/da0 4 to 7 t t [daoe0 = 1] kept [daoe0 = 0] t kept i/o port p45 to p40 4 to 7 t t t t input port
173 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pa3/a19 pa2/a18 pa1/a17 pa0/a16 4, 5 l t [ope = 0] t [ope = 1] kept t address output 6 t t [ddr ope = 0] t [ddr ope = 1] kept t [ddr = 0] input port [ddr = 1] address output 7 t t kept kept i/o port port b 4, 5 l t [ope = 0] t [ope = 1] kept t address output 6 t t [ddr ope = 0] t [ddr ope = 1] kept t [ddr = 0] input port [ddr = 1] address output 7 t t kept kept i/o port port c 4, 5 l t [ope = 0] t [ope = 1] kept t address output 6 t t [ddr ope = 0] t [ddr ope = 1] kept t [ddr = 0] input port [ddr = 1] address output 7 t t kept kept i/o port port d 4 to 6 t t t t data bus 7 t t kept kept i/o port port e 4 to 6 8-bit bus t t kept kept i/o port 16-bit bus t t t t data bus 7 t t kept kept i/o port
174 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pf7 / 4 to 6 clock output t [ddr = 0] input port [ddr = 1] h [ddr = 0] input port [ddr = 1] clock output [ddr = 0] input port [ddr = 1] clock output 7 t t [ddr = 0] input port [ddr = 1] h [ddr = 0] input port [ddr = 1] clock output [ddr = 0] input port [ddr = 1] clock output pf6/ as 4 to 6 h t [asod = 1] kept [ asod ope = 1] t [ asod ope = 1] h [asod = 1] kept [asod = 0] t [asod = 1] i/o port [asod = 0] as 7 t t kept kept i/o port pf5/ rd pf4/ hwr 4 to 6 h t [ope = 0] t [ope = 1] h t rd , hwr 7 t t kept kept i/o port pf3/ lwr / irq3 4 to 6 h t [lwrod = 1] kept [ lwrod ope = 1] t [ lwrod ope = 1] h [lwrod = 1] kept [lwrod = 0] t [lwrod = 1] i/o port [lwrod = 0] lwr 7 t t kept kept i/o port pf2/ wait / irq2 / breqo 4 to 6 t t [breqoe + waite = 0] kept [breqoe = 1] kept [breqoe = 0] and [waite ddr = 1] t [breqoe + waite = 0] kept [breqoe = 1] breqo [breqoe = 0] and [waite ddr = 1] t [breqoe + waite = 0] i/o port [breqoe = 1] breqo [breqoe = 0] and [waite ddr = 1] wait 7 t t kept kept i/o port
175 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pf1/ back / irq1 / cs5 4 to 6 t t [brle + cs25e pf1cs5s = 0] kept [ brle ddr cs25e pf1cs5s =1] and [ope = 0] t [ brle ddr cs25e pf1cs5s = 1] and [ope = 1] h [brle = 1] back l [brle + cs25e pf1cs5s = 0] i/o port [ brle ddr cs25e pf1cs5s =1] cs5 [brle = 1] back 7 t t kept kept i/o port pf0/ breq / irq0 / cs4 4 to 6 t t [brle + cs25e pf0cs4s = 0] kept [ brle ddr cs25e pf0cs4s = 1] and [ope = 0] t [ brle ddr cs25e pf0cs4s = 1] and [ope = 1] h [brle = 1] t t [brle + cs25e pf0cs4s = 0] i/o port [ brle ddr cs25e pf0cs4s = 1] cs4 [brle = 1] breq 7 t t kept kept i/o port
176 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pg4/ cs0 4, 5 h t [ddr ope = 0] t t [ddr = 0] input port 6 t [ddr ope = 1] h [ddr = 1] cs0 7 t t kept kept i/o port pg3/ cs1 / cs7 4 to 6 t t [cs167e = 0] kept [cs167e ddr = 1] t [cs167e ddr ope = 1] t [cs167e ddr ope = 1] h [cs167e = 0] kept [cs167e = 1] t [cs167e = 0] i/o port [cs167e ddr = 1] input port [cs167e css17 ddr = 1] cs1 [cs167e css17 ddr = 1] cs7 7 t t kept kept i/o port pg2/ cs2 4 to 6 t t [cs25e = 0] kept [cs25e ddr = 1] t [cs25e ddr ope = 1] t [cs25e ddr ope = 1] h [cs25e = 0] kept [cs25e = 1] t [cs25e = 0] i/o port [cs25e ddr = 1] input port [cs25e ddr = 1] cs2 7 t t kept kept i/o port
177 port name pin name mcu operating mode reset hardware standby mode software standby mode bus-released state program execution state sleep mode pg1/ cs3 / cs6 / irq7 4 to 6 t t [ css36 cs25e + css36 cs167e = 0] kept [ css36 cs25e ddr = 1] t [css36 cs167e ddr = 1] t [ css36 cs25e ddr ope = 1] t [css36 cs167e ddr ope = 1] t [ css36 cs25e ddr ope = 1] h [css36 cs167e ddr ope = 1] h [ css36 cs25e + css36 cs167e = 0] kept [ css36 cs25e + css36 cs167e = 1] t [ css36 cs25e + css36 cs167e = 0] i/o port [ css36 cs25e ddr = 1] input port [css36 cs167e ddr = 1] input port [ css36 cs25e ddr = 1] cs3 [css36 cs167e ddr = 1] cs6 7 t t kept kept i/o port pg0/ adtrg / irq6 4 to 7 t t kept kept i/o port legend h: high level l: low level t: high impedance kept: input port becomes high-impedance, output port retains state ddr: data direction register ope: output port enable waite: wait input enable brle: bus release enable breqoe: breqo pin enable ane: address n enable (n = 23 to 20) asod: as output disable cs167e: cs167 enable cs25e: cs25 enable css36: cs36 select css17: cs17 select pf1cs5s: port f1 chip select 5 select pf0cs4s: port f0 chip select 4 select lwrod: lwr output disable daoen: d/a output enable n (n = 0, 1)
178 5.14 i/o port block diagrams 5.14.1 port 1 r p1nddr c qd reset wddr1 reset wdr1 modes 4 to 6 r p1ndr c qd p1n rdr1 rpor1 internal address bus internal data bus bus controller tpu module ame bit output compare output/ pwm output enable output compare output/ pwm output input capture input wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 ame: address m enable n = 0 or 1 m = 20 or 21 figure 5.25 (a) port 1 block diagram (pins p10 and p11)
179 r p1nddr c qd reset wddr1 reset wdr1 modes 4 to 6 r p1ndr c qd p1n rdr1 rpor1 internal data bus internal address bus bus controller tpu module ame bit output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 ame: address m enable n = 2 or 3 m = 22 or 23 figure 5.25 (b) port 1 block diagram (pins p12 and p13)
180 r p1nddr c qd reset wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 internal data bus tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 n = 4 or 6 figure 5.25 (c) port 1 block diagram (pins p14 and p16)
181 r p1nddr c qd reset wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 internal data bus tpu module output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 n = 5 or 7 figure 5.25 (d) port 1 block diagram (pins p15 and p17)
182 5.14.2 port 2 r p2nddr c qd reset wddr2 reset wdr2 r p2ndr c qd p2n rdr2 rpor2 tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input internal data bus wddr2: write to p2ddr wdr2: write to p2dr rdr2: read p2dr rpor2: read port 2 n = 0 to 7 figure 5.26 port 2 block diagram (pins p2n)
183 5.14.3 port 3 r p3nddr c qd reset wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 internal data bus sci module serial transmit enable serial transmit data p3ndr reset wodr3 r c qd p3nodr * 1 * 2 wddr3: write to p3ddr wdr3: write to p3dr wodr3: write to p3odr rdr3: read p3dr rpor3: read port 3 rodr3: read p3odr n = 0 or 1 notes: 1. output enable signal 2. open drain control signal figure 5.27 (a) port 3 block diagram (pins p30 and p31)
184 r p3nddr c qd reset wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 internal data bus sci module serial receive data enable serial receive data p3ndr reset wodr3 r c qd p3nodr * 1 * 2 wddr3: write to p3ddr wdr3: write to p3dr wodr3: write to p3odr rdr3: read p3dr rpor3: read port 3 rodr3: read p3odr n = 2 or 3 notes: 1. output enable signal 2. open drain control signal figure 5.27 (b) port 3 block diagram (pins p32 and p33)
185 r p3nddr c qd reset wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 internal data bus sci module serial clock output enable interrupt controller irq interrupt input p3ndr reset wodr3 r c qd p3nodr * 1 * 2 serial clock input wddr3: write to p3ddr wdr3: write to p3dr wodr3: write to p3odr rdr3: read p3dr rpor3: read port 3 rodr3: read p3odr n = 4 or 5 notes: 1. output enable signal 2. open drain control signal serial clock output serial clock input enable figure 5.27 (c) port 3 block diagram (pins p34 and p35)
186 5.14.4 port 4 p4n rpor4 internal data bus a/d converter module analog input rpor4: read port 4 n = 0 to 5 figure 5.28 (a) port 4 block diagram (pins p40 to p45) rpor4: read port 4 n = 6 or 7 p4n rpor4 internal data bus a/d converter module analog input d/a converter module output enable analog output figure 5.28 (b) port 4 block diagram (pins p46 and p47)
187 5.14.5 port a r panpcr c qd reset wpcra reset wdra r c qd pan rdra rodra rpora internal address bus pandr reset wddra r modes 6 and 7 modes 4 and 5 c qd panddr reset wodra rpcra r c qd panodr * 1 * 2 mode 7 modes 4 to 6 internal data bus wddra: write to paddr wdra: write to padr wodra: write to paodr wpcra: write to papcr rdra: read padr rpora: read port a rodra: read paodr rpcra: read papcr n = 0 to 3 notes: 1. output enable signal 2. open drain control signal figure 5.29 port a block diagram (pins pa0, pa1, pa2, and pa3)
188 5.14.6 port b r pbnpcr c qd reset wpcrb reset wdrb r c qd pbn rdrb rporb internal address bus pbndr reset wddrb r c qd pbnddr rpcrb mode 7 modes 4 to 6 internal data bus modes 4 and 5 modes 6 and 7 wddrb: write to pbddr wdrb: write to pbdr wpcrb: write to pbpcr rdrb: read pbdr rporb: read port b rpcrb: read pbpcr n = 0 to 7 figure 5.30 port b block diagram (pins pbn)
189 5.14.7 port c r pcnpcr c qd reset wpcrc reset wdrc r c qd pcn rdrc rporc internal address bus pcndr reset wddrc r c qd pcnddr rpcrc mode 7 modes 4 to 6 internal data bus modes 4 and 5 modes 6 and 7 wddrc: write to pcddr wdrc: write to pcdr wpcrc: write to pcpcr rdrc: read pcdr rporc: read port c rpcrc: read pcpcr n = 0 to 7 figure 5.31 port c block diagram (pins pcn)
190 5.14.8 port d r pdnpcr c qd reset wpcrd reset wdrd r c qd pdn rdrd rpord external address upper write pdndr wddrd c qd pdnddr rpcrd mode 7 modes 4 to 6 external address write modes 4 to 6 mode 7 reset r external address upper read external address lower read internal upper data bus internal lower data bus wddrd: write to pdddr wdrd: write to pddr wpcrd: write to pdpcr rdrd: read pddr rpord: read port d rpcrd: read pdpcr n = 0 to 7 external address lower write figure 5.32 port d block diagram (pins pdn)
191 5.14.9 port e r penpcr c qd reset wpcre reset wdre r c qd pen rdre rpore pendr wddre c qd penddr rpcre modes 4 to 6 reset r external address lower read internal upper data bus internal lower data bus external address write 8-bit bus mode mode 7 bus controller modes 4 to 6 wddre: write to peddr wdre: write to pedr wpcre: write to pepcr rdre: read pedr rpore: read port e rpcre: read pepcr n = 0 to 7 figure 5.33 port e block diagram (pins pen)
192 5.14.10 port f r pf0ddr c qd reset wddrf reset wdrf r c qd pf0 rdrf rporf bus request input pf0dr bus controller brle bit chip select interrupt controller irq interrupt input port cs25e bit pf0cs4s bit modes 4 to 6 internal data bus wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f cs25e: cs25 enable pf0cs4s: port f0 chip select 4 select brle: bus release enable figure 5.34 (a) port f block diagram (pin pf0)
193 wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f cs25e: cs25 enable pf1cs5s: port f1 chip select 5 select brle: bus release enable r pf1ddr c qd reset wddrf modes 4 to 6 reset wdrf r pf1dr c qd pf1 rdrf rporf bus controller brle bit chip select internal data bus bus request acknowledge output port cs25e bit pf1cs5s bit interrupt controller irq interrupt input figure 5.34 (b) port f block diagram (pin pf1)
194 r pf2ddr c qd reset wddrf reset wdrf r pf2dr c qd pf2 rdrf rporf bus request output enable wait enable wait input irq interupt input bus controller interrupt controller modes 4 to 6 modes 4 to 6 internal data bus wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f bus request output figure 5.34 (c) port f block diagram (pin pf2)
195 r pf3ddr c qd reset wddrf reset wdrf r pf3dr c qd pf3 rdrf rporf bus controller lwr output interrupt controller irq interrupt input lwrod bit mode 7 modes 4 to 6 internal data bus modes 4 to 6 wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f lwrod: lwr output disable figure 5.34 (d) port f block diagram (pin pf3)
196 r pf4ddr c qd reset wddrf reset wdrf r pf4dr c qd pf4 rdrf rporf bus controller hwr output modes 4 to 6 modes 4 to 6 mode 7 internal data bus wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f figure 5.34 (e) port f block diagram (pin pf4)
197 r pf5ddr c qd reset wddrf reset wdrf r pf5dr c qd pf5 rdrf rporf bus controller rd output modes 4 to 6 modes 4 to 6 mode 7 internal data bus wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f figure 5.34 (f) port f block diagram (pin pf5)
198 r pf6ddr c qd reset wddrf modes 4 to 6 modes 4 to 6 mode 7 reset wdrf r pf6dr c qd pf6 rdrf rporf bus controller as output internal data bus asod bit wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f asod: as output disable figure 5.34 (g) port f block diagram (pin pf6)
199 d wddrf reset reset wdrf r pf7dr c qd pf7 rdrf rporf r s c qd pf7ddr internal data bus modes 4 to 6 mode 7 wddrf: write to pfddr wdrf: write to pfdr rdrf: read pfdr rporf: read port f figure 5.34 (h) port f block diagram (pin pf7)
200 5.14.11 port g r pg0ddr c qd reset wddrg reset wdrg r pg0dr c qd pg0 rdrg rporg a/d convereter a/d converter external trigger input interrput controller irq figure 5.35 (a) port g block diagram (pin pg0)
201 r pg1ddr c qd reset wddrg reset wdrg r pg1dr c qd pg1 rdrg rporg bus controller chip select 3 chip select 6 port cs167e bit cs25e bit css36 bit mode 7 internal data bus modes 4 to 6 wddrg: write to pgddr wdrg: write to pgdr rdrg: read pgdr rporg: read port g cs25e: cs25 enable cs167e: cs167 enable css36: cs36 select figure 5.35 (b) port g block diagram (pin pg1)
202 r pg2ddr c qd reset wddrg reset wdrg r pg2dr c qd pg2 rdrg rporg bus controller port chip select 2 mode 7 internal data bus cs25e bit modes 4 to 6 wddrg: write to pgddr wdrg: write to pgdr rdrg: read pgdr rporg: read port g cs25e: cs25 enable figure 5.35 (c) port g block diagram (pin pg2)
203 wddrg: write to pgddr wdrg: write to pgdr rdrg: read pgdr rporg: read port g cs167e: cs167 enable css17: cs17 select r pg3ddr c qd reset wddrg reset wdrg r pg3dr c qd pg3 rdrg rporg bus controller chip select 1 chip select 7 port cs167e bit css17 bit mode 7 internal data bus modes 4 to 6 figure 5.35 (d) port g block diagram (pin pg3)
204 qd wddrg reset reset wdrg r pg4dr c qd pg 4 rdrg rporg bus controller chip select 0 mode 7 modes 4 to 6 modes 4 and 5 modes 6 and 7 d sr c q pg4ddr internal data bus wddrg: write to pgddr wdrg: write to pgdr rdrg: read pgdr rporg: read port g d figure 5.35 (e) port g block diagram (pin pg4)
205 section 6 supporting module block diagrams 6.1 interrupt controller 6.1.1 features ? selection of two interrupt control modes ? eight priority levels can be set for each module with ipr ? independent vector addresses (nmi, irq7 to irq0 ) ? nine external interrupt pins ? dtc activation control 6.1.2 block diagram syscr nmi input irq input internal interrupt source swdtend to tei intm1 intm0 nmieg nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination i i2 to i0 ccr exr cpu legend iscr: irq sense control register ier: irq enable register isr: irq status register ipr: interrupt priority register syscr: system control register vector number interrupt request figure 6.1 block diagram of interrupt controller
206 6.1.3 pins table 6.1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 7 to 0 irq7 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 6.2 data transfer controller 6.2.1 features ? transfer possible over any number of channels ? variety of transfer modes, including normal, repeat, and block transfer ? direct specification of 16-mbyte address space possible ? byte or word can be selected as the transfer unit ? a cpu interrupt can be requested for an interrupt that activates the dtc ? can be activated by software ? module stop mode can be set ? dtc register information is located in on-chip ram
207 6.2.2 block diagram internal address bus dtcera to dtcere dtvecr interrupt controller dtc on-chip ram internal data bus register information control logic dtc activation request cpu interrupt request mra mrb cra crb dar sar interrupt request legend mra, mrb: dtc mode registers a and b cra, crb: dtc transfer count registers a and b sar: dtc source address register dar: dtc destination address register dtcera to dtcere: dtc enable registers a to e dtvecr: dtc vector register note: the rame bit in syscr must be set to 1 when the dtc is used. figure 6.2 block diagram of dtc
208 6.3 16-bit timer pulse unit 6.3.1 features ? comprises six 16-bit timer channels ? maximum 16 pulse inputs/outputs ? selection of 8 counter input clocks for each channel ? compare match, input capture, counter clear operation, synchronous operation, and pwm mode can be set for each channel ? buffer operation can be set for channels 0 and 3 ? phase counting mode can be set independently for each of channels 1, 2, 4, and 5 ? cascaded operation possible by connecting two 16-bit counter channels to form a 32-bit counter ? fast access via internal 16-bit bus ? a/d converter conversion start trigger can be generated ? module stop mode can be set
209 6.3.2 block diagram channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb channel 5 tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 0 to 2 channel 2 tmdr tsr tcr tior tier tgra tcnt tgrb bus interface common tsyr control logic tstr [input/output pins] tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 [clock input] ?1 ?4 ?16 ?64 ?256 ?1024 ?4096 tclka tclkb tclkc tclkd [input/output pins] tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 [interrupt request signals] channel 3: channel 4: channel 5: [interrupt request signals] channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal tgra tcnt tgrb tgrc channel 0 tmdr tsr tcr tiorh tier tgrd tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: figure 6.3 block diagram of tpu
210 6.3.3 pins table 6.2 tpu pins channel name symbol i/o function all clock input a tclka input external clock a input pin (channel 1 and 5 phase counting mode a-phase input) clock input b tclkb input external clock b input pin (channel 1 and 5 phase counting mode b-phase input) clock input c tclkc input external clock c input pin (channel 2 and 4 phase counting mode a-phase input) clock input d tclkd input external clock d input pin (channel 2 and 4 phase counting mode b-phase input) 0 input capture/out compare match a0 tioca0 i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match b0 tiocb0 i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match c0 tiocc0 i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match d0 tiocd0 i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match a1 tioca1 i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match b1 tiocb1 i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match a2 tioca2 i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match b2 tiocb2 i/o tgr2b input capture input/output compare output/pwm output pin 3 input capture/out compare match a3 tioca3 i/o tgr3a input capture input/output compare output/pwm output pin input capture/out compare match b3 tiocb3 i/o tgr3b input capture input/output compare output/pwm output pin input capture/out compare match c3 tiocc3 i/o tgr3c input capture input/output compare output/pwm output pin input capture/out compare match d3 tiocd3 i/o tgr3d input capture input/output compare output/pwm output pin
211 channel name symbol i/o function 4 input capture/out compare match a4 tioca4 i/o tgr4a input capture input/output compare output/pwm output pin input capture/out compare match b4 tiocb4 i/o tgr4b input capture input/output compare output/pwm output pin 5 input capture/out compare match a5 tioca5 i/o tgr5a input capture input/output compare output/pwm output pin input capture/out compare match b5 tiocb5 i/o tgr5b input capture input/output compare output/pwm output pin 6.4 8-bit timer 6.4.1 features ? two-channel timer using 8-bit counters as base ? selection of four counter input clocks ? counter clearing can be specified ? timer output by combination of two compare match signals ? cascaded operation possible by connecting both counter channels to form a 16-bit counter ? three interrupt sources for each channel ? a/d converter conversion start trigger can be generated ? module stop mode can be set
212 6.4.2 block diagram external clocks internal clocks /8 /64 /8192 clock 1 clock 0 compare match a1 compare match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo0 tmri0 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci0 tmci1 tcnt0 overflow 1 overflow 0 compare match b1 compare match b0 tmo1 tmri1 clock selection control logic clear 0 a/d conversion start request signal figure 6.4 block diagram of 8-bit timer
213 6.4.3 pins table 6.3 8-bit timer pins channel name symbol i/o function 0 timer output pin 0 tmo0 output compare match output timer clock input pin 0 tmci0 input counter external clock input timer reset input pin 0 tmri0 input counter external reset input 1 timer output pin 1 tmo1 output compare match output timer clock input pin 1 tmci1 input counter external clock input timer reset input pin 1 tmri1 input counter external reset input
214 6.5 watchdog timer 6.5.1 features ? switchable between watchdog timer mode and interval timer mode ? wdtovf output in watchdog timer mode ? interrupt generation when counter overflows in interval timer mode ? selection of eight counter input clocks 6.5.2 block diagram overflow interrupt control wovi (interrupt request signal) wdtovf * 2 internal reset signal * 1 reset control rstcsr tcnt tscr /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock selection internal clocks bus interface module bus internal bus wdt legend tcsr: timer control/status register tcnt: timer counter rstcsr: reset control/status register 1. the internal reset signal can be generated by means of a register setting. 2. the wdtovf figure 6.5 block diagram of wdt
215 6.5.3 pins table 6.4 wdt pin name symbol i/o function watchdog timer overflow wdtovf * output outputs counter overflow signal in watchdog timer mode note: * the wdtovf 6.6 serial communication interface 6.6.1 features ? two on-chip channels in the h8s/2319 and h8s/2318 series ? selection of synchronous or asynchronous serial communication mode ? full-duplex communication capability ? selection of lsb-first or msb-first transfer ? built-in baud rate generator allows any bit rate to be selected ? selection of transmit/receive clock source ? four interrupts (eri, rxi, txi, and tei), of which rxi and txi can activate the dtc ? module stop mode can be set
216 6.6.2 block diagram rxd txd sck clock /4 /16 /64 tei txi rxi eri scmr ssr scr smr transmission/ reception control baud rate generator brr module data bus bus interface internal data bus rdr tsr rsr parity generation tdr parity check external clock legend scmr: smart card mode register rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register figure 6.6 block diagram of sci
217 6.6.3 pins table 6.5 sci pins channel name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output
218 6.7 smart card interface 6.7.1 features ? ic card interface conforming to iso/iec7816-3 supported as sci extension function ? switching between normal sci and smart card interface by means of register setting ? built-in baud rate generator allows any bit rate to be selected ? three interrupts (txi, rxi, and eri), of which rxi and txi can activate the dtc 6.7.2 block diagram bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock /4 /16 /64 txi rxi eri smr legend scmr: smart card mode register rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register figure 6.7 block diagram of smart card interface
219 6.7.3 pins table 6.6 smart card interface pins channel name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 6.8 a/d converter (8 analog input channel version) 6.8.1 features ? 10-bit resolution ? 8 input channels ? settable analog conversion voltage range ? conversion time: 6.7 ? per channel (at 20 mhz operation) ? selection of single mode or scan mode as operating mode ? four data registers ? sample-and-hold function ? three kinds of conversion start (software, timer conversion start trigger, or adtrg pin) ? a/d conversion end interrupt request generation ? module stop mode can be set
220 6.8.2 block diagram module data bus control circuit internal data bus 10-bit d/a comparator + sample-and-hold circuit bus interface addra successive-approximations register multiplexer av cc adtrg figure 6.8 block diagram of a/d converter
221 6.8.3 pins table 6.7 a/d converter pins name symbol i/o function analog power supply pin av cc input analog circuit power supply analog ground pin av ss input analog circuit ground and reference voltage reference voltage pin v ref input a/d conversion reference voltage analog input pin 0 an0 input group 0 analog input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input group 1 analog input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input a/d external trigger input pin adtrg
222 6.9 d/a converter 6.9.1 features ? 8-bit resolution ? two output channels ? maximum conversion time of 10 ? (with 20 pf capacitive load) ? output voltage of 0 v to v ref ? d/a output hold function in software standby mode ? module stop mode can be set 6.9.2 block diagram module data bus internal data bus v ref av cc da 1 da 0 av ss 8-bit d/a control circuit dacr bus interface dadr0 dadr1 legend dacr: d/a control register dadr0, dadr1: d/a data registers 0 and 1 figure 6.9 block diagram of d/a converter
223 6.9.3 pins table 6.8 d/a converter pins name symbol i/o function analog power supply pin av cc input analog circuit power supply analog ground pin av ss input analog circuit ground and reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output reference voltage pin v ref input analog circuit reference voltage
224 6.10 ram 6.10.1 features ? eight kbytes of on-chip high-speed static ram in the h8s/2319, h8s/2318, h8s/2317, h8s/2316, h8s/2315, and h8s/2312, and two kbytes in the h8s/2313, h8s/2311, and h8s/2310 ? connected to the cpu by a 16-bit data bus, enabling one-state access to both byte data and word data ? can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr) 6.10.2 block diagram internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffdc00 h'ffdc02 h'ffdc04 h'fffbfe h'ffdc01 h'ffdc03 h'ffdc05 h'fffbff figure 6.10 block diagram of ram (8 kbytes)
225 6.11 rom (h8s/2319) 6.11.1 features ? connected to the bus master by a 16-bit data bus, enabling one-state access to both byte data and word data ? the flash memory version (h8s/2319 f-ztat) can be erased and programmed with a prom programmer, as well as on-board 6.11.2 block diagrams internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'07fffe h'000001 h'000003 h'07ffff figure 6.11 block diagram of flash memory (512 kbytes)
226 module bus bus interface/controller flash memory (512 kbytes) operating mode internal address bus internal data bus (16 bits) mode pins flmcr2 ebr1 ebr2 ramer flmcr1 syscr2 legend flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ebr2: erase block register 2 ramer: ram emulation register syscr2: system control register 2 figure 6.12 block diagram of flash memory
227 6.12 rom 6.12.1 features ? connected to the bus master by a 16-bit data bus, enabling one-state access to both byte data and word data ? the flash memory version (256 kbytes in the h8s/2318 f-ztat and 384 kbytes in the h8s/2315 f-ztat) can be erased and programmed with a prom programmer, as well as on- board ? the h8s/2318 has 256 kbytes, the h8s/2317 128 kbytes, the h8s/2316 and h8s/2313 64 kbytes, and the h8s/2311 32 kbytes, of on-chip mask rom 6.12.2 block diagrams internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'03fffe h'000001 h'000003 h'03ffff figure 6.13 block diagram of mask rom (256 kbytes)
228 module bus bus interface/controller flash memory (256 kbytes/384 kbytes) operating mode internal address bus internal data bus (16 bits) fwe pin mode pins flmcr2 ebr1 ebr2 ramer flmcr1 syscr2 legend flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ebr2: erase block register 2 ramer: ram emulation register syscr2: system control register 2 figure 6.14 block diagram of flash memory
229 6.13 clock pulse generator 6.13.1 features ? comprises an oscillator, duty correction circuit, medium-speed clock divider, and bus master clock selection circuit ? generates system clock (?, bus master clock, and internal clock ? allows switching between medium-speed mode and variable clock division function 6.13.2 block diagram extal xtal duty correction circuit oscillator medium- speed clock divider system clock to pin internal clock to on-chip supporting modules /2 to /32 sck2 to sck0 div sckcr bus master clock selection circuit bus master clock to cpu and dtc figure 6.15 block diagram of clock pulse generator
230
231 section 7 electrical characteristics note: please contact a hitachi sales agency for the electrical characteristics of the h8s/2319 f-ztat version. 7.1 electrical characteristics of mask rom version (h8s/2318, h8s/2317, h8s/2316, h8s/2313, h8s/2311) and romless version (h8s/2312, h8s/2310) 7.1.1 absolute maximum ratings table 7.1 lists the absolute maximum ratings. table 7.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?.3 to +4.3 v input voltage (except port 4) v in ?.3 to v cc +0.3 v input voltage (port 4) v in ?.3 to av cc +0.3 v reference power supply voltage v r e f ?.3 to av cc +0.3 v analog power supply voltage av cc ?.3 to +4.3 v analog input voltage v an ?.3 to av cc +0.3 v operating temperature t opr regular specifications: ?0 to +75 ? wide-range specifications: ?0 to +85 ? storage temperature t stg ?5 to +125 ? caution: permanent damage to the chip may result if absolute maximum ratings are exceeded.
232 7.1.2 dc characteristics table 7.2 dc characteristics conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide- range specifications) item symbol min typ max unit test conditions schmitt ports 1, 2, vt v cc 0.2 v trigger input irq0 to irq7 vt + v cc 0.7 v voltage vt + ?vt v cc 0.07 v input high voltage res , stby , nmi, md2 to md0 v ih v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v ports 3, a to g 2.2 v cc + 0.3 v port 4 2.2 av cc + 0.3 v input low voltage res , stby , md2 to md0 v il ?.3 v cc 0.1 v nmi, extal, ports 3, 4, a to g ?.3 v cc 0.2 v output high all output pins v oh v cc ?0.5 v i oh = ?00 a voltage v cc ?1.0 v i oh = ? ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma input leakage res | i in | 10.0 av in = 0.5 to v cc ?0.5 v current stby , nmi, md2 to md0 1.0 a port 4 1.0 av in = 0.5 to av cc ?0.5 v three-state leakage current (off state) ports 1, 2, 3, a to g | i tsi | 1.0 av in = 0.5 to v cc ?0.5 v
233 item symbol min typ max unit test conditions input pull-up mos current ports a to e i p 10 300 av in = 0v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25? current normal operation i cc * 4 35 (3.0 v) 80 ma f = 20 mhz dissipation * 2 50 (3.3 v) 100 ma f = 25 mhz sleep mode 25 (3.0 v) 64 ma f = 20 mhz 35 (3.3 v) 80 ma f = 25 mhz standby mode * 3 0.01 10 at a 50? 80 50? < t a analog power during a/d and d/a conversion ai cc 0.2 (3.0 v) 2.0 ma supply voltage idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 3.0 ma supply voltage idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open . connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. current dissipation values are for v ih min = v cc ?0.2 v and v il max = 0.2 v with all output pins unloaded and all mos input pull-ups in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 1.10 (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + 0.88 (ma/(mhz v)) v cc f (sleep mode)
234 table 7.3 permissible output currents conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80ma permissible output high current (per pin) all output pins ? oh 2.0 ma permissible output high current (total) total of all output pins ? oh 40ma note: to protect chip reliability, do not exceed the output current values in table 7.3. 7.1.3 ac characteristics 3 v r l r h c chip output pin c = 50 pf: ports 1, a to f c = 30 pf: ports 2, 3, g r l = 2.4 k ? r h = 12 k ? input/output timing measurement level: 1.5 v (v cc = 2.7 v to 3.6 v) figure 7.1 output load circuit
235 (1) clock timing table 7.4 clock timing condition a: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions clock cycle time t cyc 50 500 40 500 ns figure 7.2 clock pulse high width t ch 20 15 ns clock pulse low width t cl 20 15 ns clock rise time t cr 5 5ns clock fall time t cf 5 5ns reset oscillation stabilization time (crystal) t osc1 10 10 ms figure 7.3 software standby oscillation stabilization time (crystal) t osc2 10 10 ms external clock output stabilization delay time t dext 500 500 s figure 7.3
236 t cr t cl t cf t ch t cyc figure 7.2 system clock timing t osc1 t osc1 extal v cc stby res t dext t dext nmi figure 7.3 oscillation stabilization timing
237 (2) control signal timing table 7.5 control signal timing condition a: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions res setup time t ress 200 200 ns figure 7.4 res pulse width t resw 20 20 t cyc nmi setup time t nmis 150 150 ns figure 7.5 nmi hold time t nmih 10 10 nmi pulse width (in recovery from software standby mode) t nmiw 200 200 irq setup time t irqs 150 150 ns irq hold time t irqh 10 10 irq pulse width (in recovery from software standby mode) t irqw 200 200
238 t resw t ress t ress res figure 7.4 reset input timing t irqs irq edge input t irqh t nmis t nmih t irqs irq level input nmi irq t nmiw t irqw figure 7.5 interrupt input timing
239 (3) bus timing table 7.6 bus timing condition a: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b item symbol min max min max unit test conditions address delay time t ad 20 20 ns figures 7.6 to 7.10 address setup time t as 0.5 t cyc 15 0.5 t cyc 15 ns address hold time t ah 0.5 t cyc 10 0.5 t cyc 8 ns cs delay time 1 t csd1 20 15 ns as delay time t asd 20 15 ns rd delay time 1 t rsd1 20 15 ns rd delay time 2 t rsd2 20 15 ns read data setup time t rds 15 15 ns read data hold time t rdh 0 0 ns read data access time 1 t acc1 1.0 t cyc 25 1.0 t cyc 20 ns read data access time 2 t acc2 1.5 t cyc 25 1.5 t cyc 20 ns read data access time 3 t acc3 2.0 t cyc 25 2.0 t cyc 20 ns read data access time 4 t acc4 2.5 t cyc 25 2.5 t cyc 20 ns read data access time 5 t acc5 3.0 t cyc 25 3.0 t cyc 20 ns
240 condition a condition b item symbol min max min max unit test conditions wr delay time 1 t wrd1 20 15 ns figures 7.6 to 7.10 wr delay time 2 t wrd2 20 15 ns wr pulse width 1 t wsw1 1.0 t cyc 20 1.0 t cyc 15 ns wr pulse width 2 t wsw2 1.5 t cyc 20 1.5 t cyc 15 ns write data delay time t wdd 30 20 ns write data setup time t wds 0.5 t cyc 20 0.5 t cyc 15 ns write data hold time t wdh 0.5 t cyc 10 0.5 t cyc 8 ns wait setup time t wts 30 25 ns figure 7.8 wait hold time t wth 5 5 ns breq setup time t brqs 30 30 ns figure 7.11 back delay time t bacd 15 15 ns bus floating time t bzd 50 40 ns breqo delay time t brqod 30 25 ns figure 7.12
241 a23 to a0 cs7 to cs0 as t rsd2 t as t ah t csd1 t acc2 t rsd1 t asd t asd t ad t acc3 t wrd2 t wrd2 t wsw1 t wdd t wdh t 1 t 2 rd (read) d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t rds t ah t as t as t rdh figure 7.6 basic bus timing (2-state access)
242 a23 to a0 cs7 to cs0 as t rsd2 t as t ah t csd1 t acc4 t rsd1 t asd t asd t ad t acc5 t wrd2 t wrd1 t wsw2 t wdd t wdh t 1 t 3 rd (read) d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t wds t 2 t rds t as t ah t rdh figure 7.7 basic bus timing (3-state access)
243 a23 to a0 cs7 to cs0 as t wth t 1 t 2 rd (read) d15 to d0 (read) hwr to lwr (write) d15 to d0 (write) wait t w t 3 t wts t wth t wts figure 7.8 basic bus timing (3-state access, 1 wait)
244 a23 to a0 cs0 as t rsd2 t as t ah t asd t asd t ad t acc3 t rds t rdh t 1 t 2 rd (read) d15 to d0 (read) t 2 or t 3 t 1 figure 7.9 burst rom access timing (2-state access)
245 t ad t acc1 t rds t rdh t 1 t 2 or t 3 t 1 a23 to a0 cs0 as rd (read) d15 to d0 (read) t rsd2 figure 7.10 burst rom access timing (1-state access)
246 breq back t bacd t bzd a23 to a0, cs7 to cs0 , as , rd , hwr , lwr t bacd t bzd t brqs t brqs figure 7.11 external bus release timing breqo t brqod t brqod figure 7.12 external bus request output timing
247 (4) timing of on-chip supporting modules table 7.7 timing of on-chip supporting modules condition a: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions i/o ports output data delay time t pwd 50 40 ns figure 7.13 input data setup time t prs 30 25 input data hold time t prh 30 25 tpu timer output delay time t tocd 50 40 ns figure 7.14 timer input setup time t tics 30 25 timer clock input setup time t tcks 30 25 ns figure 7.15 timer clock pulse width single-edge specification t tckwh 1.5 1.5 t cyc both-edge specification t tckwl 2.5 2.5 8-bit timer timer output delay time t tmod 50 40 ns figure 7.16 timer reset input setup time t tmrs 30 25 ns figure 7.18 timer clock input setup time t tmcs 30 25 ns figure 7.17 timer clock pulse width single-edge specification t tmcwh 1.5 1.5 t cyc both-edge specification t tmcwl 2.5 2.5 wdt overflow output delay time t wovd 50 40 ns figure 7.19
248 condition a condition b test item symbol min max min max unit conditions sci input clock asynchronous t scyc 4 4 t cyc figure 7.20 cycle synchronous 6 6 input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 transmit data delay time t txd 50 40 ns figure 7.21 receive data setup time (synchronous) t rxs 50 40 ns receive data hold time (synchronous) t rxh 50 40 ns a/d converter trigger input setup time t trgs 30 30 ns figure 7.22 ports 1 to 4, a to g (read) t prs t 1 t 2 t pwd t prh ports 1 to 3, a to g (write) figure 7.13 i/o port input/output timing
249 t tics t tocd output compare output * input capture input * note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 7.14 tpu input/output timing t tcks t tcks tclka to tclkd t tckwh t tckwl figure 7.15 tpu clock input timing t tmod tmo0, tmo1 figure 7.16 8-bit timer output timing
250 t tmcs t tmcs tmci0, tmci1 t tmcwh t tmcwl figure 7.17 8-bit timer clock input timing t tmrs tmri0, tmri1 figure 7.18 8-bit timer reset input timing t wovd wdtovf t wovd figure 7.19 wdt output timing t scyc t sckr t sckw sck0, sck1 t sckf figure 7.20 sck clock input timing
251 sck0, sck1 txd0, txd1 (transmit data) rxd0, rxd1 (receive data) t txd t rxh t rxs figure 7.21 sci input/output timing (synchronous mode) t trgs adtrg figure 7.22 a/d converter external trigger input timing
252 7.1.4 a/d conversion characteristics table 7.8 a/d conversion characteristics condition a: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to 75 c (regular specifications), t a = 40 c to 85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 25 mhz, t a = 20 c to 75 c (regular specifications), t a = 40 c to 85 c (wide-range specifications) condition a condition b item min typ max min typ max unit resolution 10 10 10 10 10 10 bits conversion time 6.7 10.6 s analog input capacitance 20 20 pf permissible signal source impedance 5 5k ? nonlinearity error 5.5 5.5 lsb offset error 5.5 5.5 lsb full-scale error 5.5 5.5 lsb quantization error 0.5 0.5 lsb absolute accuracy 6.0 6.0 lsb
253 7.1.5 d/a conversion characteristics table 7.9 d/a conversion characteristics condition a: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, = 2 mhz to 20 mhz, t a = 20 c to 75 c (regular specifications), t a = 40 c to 85 c (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, = 2 mhz to 25 mhz, t a = 20 c to 75 c (regular specifications), t a = 40 c to 85 c (wide-range specifications) condition a condition b test item min typ max min typ max unit conditions resolution 8 8 8 8 8 8 bits conversion time 10 10 s 20 pf capacitive load absolute accuracy 2.0 3.0 2.0 3.0 lsb 2 m ? resistive load 2.0 2.0 lsb 4 m ? resistive load
254 7.2 electrical characteristics of mask rom version (h8s/2318, h8s/2317) in low-voltage operation 7.2.1 absolute maximum ratings table 7.10 lists the absolute maximum ratings. table 7.10 absolute maximum ratings item symbol value unit power supply voltage v cc ?.3 to +4.3 v input voltage (except port 4) v in ?.3 to v cc +0.3 v input voltage (port 4) v in ?.3 to av cc +0.3 v reference power supply voltage v r e f ?.3 to av cc +0.3 v analog power supply voltage av cc ?.3 to +4.3 v analog input voltage v an ?.3 to av cc +0.3 v operating temperature t opr regular specifications: ?0 to +75 ? storage temperature t stg ?5 to +125 ? caution: permanent damage to the chip may result if absolute maximum ratings are exceeded.
255 7.2.2 dc characteristics table 7.11 dc characteristics condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications) item symbol min typ max unit test conditions schmitt ports 1, 2, vt v cc 0.2 v trigger input irq0 to irq7 vt + v cc 0.7 v voltage vt + ?vt v cc 0.07 v input high voltage res , stby , nmi, md2 to md0 v ih v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v ports 3, a to g 2.2 v cc + 0.3 v port 4 2.2 av cc + 0.3 v input low voltage res , stby , md2 to md0 v il ?.3 v cc 0.1 v nmi, extal, ports 3, 4, a to g ?.3 v cc 0.2 v output high all output pins v oh v cc ?0.5 v i oh = ?00 a voltage v cc ?1.0 v i oh = ? ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma input leakage res | i in | 10.0 av in = 0.5 to v cc ?0.5 v current stby , nmi, md2 to md0 1.0 a port 4 1.0 av in = 0.5 to av cc ?0.5 v three-state leakage current (off state) ports 1, 2, 3, a to g | i tsi | 1.0 av in = 0.5 to v cc ?0.5 v
256 item symbol min typ max unit test conditions input pull-up mos current ports a to e i p 10 300 av in = 0v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25? current normal operation i cc * 4 18 (2.7 v) 39 ma f = 14 mhz dissipation * 2 sleep mode 12 (2.7 v) 26 ma f = 14 mhz standby mode * 3 0.01 10 at a 50? 80 50? < t a analog power during a/d and d/a conversion ai cc 0.2 (3.0 v) 2.0 ma supply voltage idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 3.0 ma supply voltage idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open . connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. current dissipation values are for v ih min = v cc ?0.2 v and v il max = 0.2 v with all output pins unloaded and all mos input pull-ups in the off state. 3. the values are for v ram v cc < 2.4 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 0.74 (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + 0.50 (ma/(mhz v)) v cc f (sleep mode)
257 table 7.12 permissible output currents condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v, t a = ?0? to +75? (regular specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80ma permissible output high current (per pin) all output pins ? oh 2.0 ma permissible output high current (total) total of all output pins ? oh 40ma note: to protect chip reliability, do not exceed the output current values in table 7.12. 7.2.3 ac characteristics 3 v r l r h c chip output pin c = 50 pf: ports 1, a to f c = 30 pf: ports 2, 3, g r l = 2.4 k ? r h = 12 k ? input/output timing measurement level: 1.5 v (v cc = 2.4 v to 3.6 v) figure 7.23 output load circuit
258 (1) clock timing table 7.13 clock timing condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 14 mhz, t a = ?0? to 75? (regular specifications) condition c item symbol min max unit test conditions clock cycle time t cyc 71 500 ns figure 7.2 clock pulse high width t ch 28 ns clock pulse low width t cl 28 ns clock rise time t cr 7.5 ns clock fall time t cf 7.5 ns reset oscillation stabilization time (crystal) t osc1 10 ms figure 7.3 software standby oscillation stabilization time (crystal) t osc2 10 ms external clock output stabilization delay time t dext 500 s figure 7.3
259 (2) control signal timing table 7.14 control signal timing condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 14 mhz, t a = ?0? to 75? (regular specifications) condition c item symbol min max unit test conditions res setup time t ress 200 ns figure 7.4 res pulse width t resw 20 t cyc nmi setup time t nmis 150 ns figure 7.5 nmi hold time t nmih 10 nmi pulse width (in recovery from software standby mode) t nmiw 200 irq setup time t irqs 150 ns irq hold time t irqh 10 irq pulse width (in recovery from software standby mode) t irqw 200
260 (3) bus timing table 7.15 bus timing condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 14 mhz, t a = ?0? to 75? (regular specifications) condition c item symbol min max unit test conditions address delay time t ad 20 ns figures 7.6 to 7.10 address setup time t as 0.5 t cyc 15 ns address hold time t ah 0.5 t cyc 15 ns cs delay time 1 t csd1 25 ns as delay time t asd 25 ns rd delay time 1 t rsd1 25 ns rd delay time 2 t rsd2 25 ns read data setup time t rds 15 ns read data hold time t rdh 0 ns read data access time 1 t acc1 1.0 t cyc 35 ns read data access time 2 t acc2 1.5 t cyc 35 ns read data access time 3 t acc3 2.0 t cyc 35 ns read data access time 4 t acc4 2.5 t cyc 35 ns read data access time 5 t acc5 3.0 t cyc 35 ns wr delay time 1 t wrd1 25 ns wr delay time 2 t wrd2 25 ns wr pulse width 1 t wsw1 1.0 t cyc 25 ns wr pulse width 2 t wsw2 1.5 t cyc 25 ns write data delay time t wdd 30 ns write data setup time t wds 0.5 t cyc 25 ns write data hold time t wdh 0.5 t cyc 15 ns wait setup time t wts 40 ns figure 7.8 wait hold time t wth 5 ns breq setup time t brqs 30 ns figure 7.11 back delay time t bacd 15 ns bus floating time t bzd 70 ns breqo delay time t brqod 40 ns figure 7.12
261 (4) timing of on-chip supporting modules table 7.16 timing of on-chip supporting modules condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 14 mhz, t a = ?0? to 75? (regular specifications) condition c item symbol min max unit test conditions i/o ports output data delay time t pwd 70 ns figure 7.13 input data setup time t prs 40 input data hold time t prh 40 tpu timer output delay time t tocd 70 ns figure 7.14 timer input setup time t tics 40 timer clock input setup time t tcks 40 ns figure 7.15 timer clock pulse width single-edge specification t tckwh 1.5 t cyc both-edge specification t tckwl 2.5 8-bit timer timer output delay time t tmod 70 ns figure 7.16 timer reset input setup time t tmrs 40 ns figure 7.18 timer clock input setup time t tmcs 40 ns figure 7.17 timer clock pulse width single-edge specification t tmcwh 1.5 t cyc both-edge specification t tmcwl 2.5 wdt overflow output delay time t wovd 70 ns figure 7.19 sci input clock asynchronous t scyc 4 t cyc figure 7.20 cycle synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr 1.5 t cyc input clock fall time t sckf 1.5 transmit data delay time t txd 70 ns figure 7.21 receive data setup time (synchronous) t rxs 70 ns receive data hold time (synchronous) t rxh 70 ns a/d converter trigger input setup time t trgs 30 ns figure 7.22
262 7.2.4 a/d conversion characteristics table 7.17 a/d conversion characteristics condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 14 mhz, t a = ?0? to 75? (regular specifications) condition c item min typ max unit resolution 10 10 10 bits conversion time 19.0 s analog input capacitance 20 pf permissible signal source impedance 5k ? nonlinearity error 7.5 lsb offset error 7.5 lsb full-scale error 7.5 lsb quantization error 0.5 lsb absolute accuracy 8.0 lsb 7.2.5 d/a conversion characteristics table 7.18 d/a conversion characteristics condition c: v cc = 2.4 v to 3.6 v, av cc = 2.4 v to 3.6 v, v ref = 2.4 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 14 mhz, t a = ?0? to 75? (regular specifications) condition c item min typ max unit conditions resolution 8 8 8 bits conversion time 10 s 20 pf capacitive load absolute accuracy 2.0 3.0 lsb 2 m ? resistive load 2.0 lsb 4 m ? resistive load
263 7.3 electrical characteristics of f-ztat version (h8s/2318) 7.3.1 absolute maximum ratings table 7.19 absolute maximum ratings ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) item symbol value unit power supply voltage v cc 0.3 to +4.3 v input voltage (fwe) v in 0.3 to v cc +0.3 v input voltage (except port 4) v in 0.3 to v cc +0.3 v input voltage (port 4) v in 0.3 to av cc +0.3 v reference power supply voltage v r e f 0.3 to av cc +0.3 v analog power supply voltage av cc 0.3 to +4.3 v analog input voltage v an 0.3 to av cc +0.3 v operating temperature t opr regular specifications: 20 to +75 * c wide-range specifications: 40 to +85 * c storage temperature t stg 55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. note: * condition a (in planning): the operating temperature ranges for flash memory programming/erasing are t a = 0 c to +tbd c (regular specifications) and t a = 0 c to +tbd c (wide-range specifications). the power-supply voltage range for flash memory programming/erasing is v cc = 3.0 v to 3.6 v. condition b: the operating temperature ranges for flash memory programming/erasing are t a = 0 c to +75 c (regular specifications) and t a = 0 c to +85 c (wide- range specifications).
264 7.3.2 dc characteristics table 7.20 (a) dc characteristics ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage ports 1, 2, irq0 to irq7 vt v cc 0.2 v vt + v cc 0.7 v vt + vt v cc 0.07 v input high voltage res , stby , nmi, md2 to md0, fwe v ih v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v ports 3, a to g 2.2 v cc + 0.3 v port 4 2.2 av cc + 0.3 v input low voltage res , stby , md2 to md0, fwe v il 0.3 v cc 0.1 v nmi, extal, ports 3, 4, a to g 0.3 v cc 0.2 v output high all output pins v oh v cc 0.5 vi oh = 200 a voltage v cc 1.0 vi oh = 1 ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma input leakage res | i in | 10.0 av in = 0.5 to v cc 0.5 v current stby , nmi, md2 to md0, fwe 1.0 a port 4 1.0 av in = 0.5 to av cc 0.5 v three-state leakage current (off state) ports 1, 2, 3, a to g | i tsi | 1.0 av in = 0.5 to v cc 0.5 v
265 item symbol min typ max unit test conditions input pull-up mos current ports a to e i p 10 300 av cc = 2.7 v to 3.6 v, v in = 0 v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25 c current normal operation i cc * 4 35 (3.0 v) 80 ma f = 20 mhz dissipation * 2 sleep mode 25 (3.0 v) 64 ma f = 20 mhz standby mode * 3 0.01 10 at a 50 c 80 50 c < t a analog power during a/d and d/a conversion ai cc 0.2 (3.0 v) 2.0 ma supply voltage idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 3.0 ma supply voltage idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open . connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. current dissipation values are for v ih min = v cc 0.2 v and v il max = 0.2 v with all output pins unloaded and all mos input pull-ups in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 1.10 (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + 0.88 (ma/(mhz v)) v cc f (sleep mode)
266 table 7.20 (b) dc characteristics ?preliminary condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage ports 1, 2, irq0 to irq7 vt v cc 0.2 v vt + v cc 0.7 v vt + vt v cc 0.07 v input high voltage res , stby , nmi, md2 to md0, fwe v ih v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v ports 3, a to g 2.2 v cc + 0.3 v port 4 2.2 av cc + 0.3 v input low voltage res , stby , md2 to md0, fwe v il 0.3 v cc 0.1 v nmi, extal, ports 3, 4, a to g 0.3 v cc 0.2 v output high all output pins v oh v cc 0.5 vi oh = 200 a voltage v cc 1.0 vi oh = 1 ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma input leakage res | i in | 10.0 av in = 0.5 to v cc 0.5 v current stby , nmi, md2 to md0, fwe 1.0 a port 4 1.0 av in = 0.5 to av cc 0.5 v three-state leakage current (off state) ports 1, 2, 3, a to g | i tsi | 1.0 av in = 0.5 to v cc 0.5 v
267 item symbol min typ max unit test conditions input pull-up mos current ports a to e i p 10 300 av cc = 3.0 v to 3.6 v, v in = 0 v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25 c current normal operation i cc * 4 50 (3.3 v) 100 ma f = 25 mhz dissipation * 2 sleep mode 35 (3.3 v) 80 ma f = 25 mhz standby mode * 3 0.01 10 at a 50 c 80 50 c < t a analog power during a/d and d/a conversion ai cc 0.2 (3.0 v) 2.0 ma supply voltage idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 3.0 ma supply voltage idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open . connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. current dissipation values are for v ih min = v cc 0.2 v and v il max = 0.2 v with all output pins unloaded and all mos input pull-ups in the off state. 3. the values are for v ram v cc < 3.0 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 1.10 (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + 0.88 (ma/(mhz v)) v cc f (sleep mode)
268 table 7.21 (a) permissible output currents ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80 ma permissible output high current (per pin) all output pins i oh 2.0 ma permissible output high current (total) total of all output pins i oh 40 ma note: to protect chip reliability, do not exceed the output current values in table 7.12 (a). table 7.21 (b) permissible output currents ?preliminary condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80 ma permissible output high current (per pin) all output pins i oh 2.0 ma permissible output high current (total) total of all output pins i oh 40 ma note: to protect chip reliability, do not exceed the output current values in table 7.12 (b).
269 7.3.3 ac characteristics (1) clock timing table 7.22 clock timing ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions clock cycle time t cyc 50 500 40 500 ns figure 7.2 clock pulse high width t ch 20 15 ns clock pulse low width t cl 20 15 ns clock rise time t cr 5 5ns clock fall time t cf 5 5ns reset oscillation stabilization time (crystal) t osc1 10 10 ms figure 7.3 software standby oscillation stabilization time (crystal) t osc2 10 10 ms external clock output stabilization delay time t dext 500 500 s figure 7.3
270 (2) control signal timing table 7.23 control signal timing ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions res setup time t ress 200 200 ns figure 7.4 res pulse width t resw 20 20 t cyc nmi setup time t nmis 150 150 ns figure 7.5 nmi hold time t nmih 10 10 nmi pulse width (in recovery from software standby mode) t nmiw 200 200 irq setup time t irqs 150 150 ns irq hold time t irqh 10 10 irq pulse width (in recovery from software standby mode) t irqw 200 200
271 (3) bus timing table 7.24 bus timing ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b item symbol min max min max unit test conditions address delay time t ad 20 20 ns figures 7.6 to 7.10 address setup time t as 0.5 t cyc 15 0.5 t cyc 15 ns address hold time t ah 0.5 t cyc 10 0.5 t cyc 8 ns cs delay time 1 t csd1 20 15 ns as delay time t asd 20 15 ns rd delay time 1 t rsd1 20 15 ns rd delay time 2 t rsd2 20 15 ns read data setup time t rds 15 15 ns read data hold time t rdh 0 0 ns read data access time 1 t acc1 1.0 t cyc 25 1.0 t cyc 20 ns read data access time 2 t acc2 1.5 t cyc 25 1.5 t cyc 20 ns read data access time 3 t acc3 2.0 t cyc 25 2.0 t cyc 20 ns read data access time 4 t acc4 2.5 t cyc 25 2.5 t cyc 20 ns read data access time 5 t acc5 3.0 t cyc 25 3.0 t cyc 20 ns
272 condition a condition b item symbol min max min max unit test conditions wr delay time 1 t wrd1 20 15 ns figures 7.6 to 7.10 wr delay time 2 t wrd2 20 15 ns wr pulse width 1 t wsw1 1.0 t cyc 20 1.0 t cyc 15 ns wr pulse width 2 t wsw2 1.5 t cyc 20 1.5 t cyc 15 ns write data delay time t wdd 30 20 ns write data setup time t wds 0.5 t cyc 20 0.5 t cyc 15 ns write data hold time t wdh 0.5 t cyc 10 0.5 t cyc 8 ns wait setup time t wts 30 25 ns figure 7.8 wait hold time t wth 5 5 ns breq setup time t brqs 30 30 ns figure 7.11 back delay time t bacd 15 15 ns bus floating time t bzd 50 40 ns breqo delay time t brqod 30 25 ns figure 7.12
273 (4) timing of on-chip supporting modules table 7.25 timing of on-chip supporting modules ?reliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions i/o ports output data delay time t pwd 50 40 ns figure 7.13 input data setup time t prs 30 25 input data hold time t prh 30 25 tpu timer output delay time t tocd 50 40 ns figure 7.14 timer input setup time t tics 30 25 timer clock input setup time t tcks 30 25 ns figure 7.15 timer clock pulse width single-edge specification t tckwh 1.5 1.5 t cyc both-edge specification t tckwl 2.5 2.5 8-bit timer timer output delay time t tmod 50 40 ns figure 7.16 timer reset input setup time t tmrs 30 25 ns figure 7.18 timer clock input setup time t tmcs 30 25 ns figure 7.17 timer clock pulse width single-edge specification t tmcwh 1.5 1.5 t cyc both-edge specification t tmcwl 2.5 2.5
274 condition a condition b test item symbol min max min max unit conditions sci input clock asynchronous t scyc 4 4 t cyc figure 7.20 cycle synchronous 6 6 input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 transmit data delay time t txd 50 40 ns figure 7.21 receive data setup time (synchronous) t rxs 50 40 ns receive data hold time (synchronous) t rxh 50 40 ns a/d converter trigger input setup time t trgs 30 30 ns figure 7.22
275 7.3.4 a/d conversion characteristics table 7.26 a/d conversion characteristics ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b item min typ max min typ max unit resolution 10 10 10 10 10 10 bits conversion time 6.7 10.6 s analog input capacitance 20 20 pf permissible signal source impedance 5 5k ? nonlinearity error 5.5 5.5 lsb offset error 5.5 5.5 lsb full-scale error 5.5 5.5 lsb quantization error 0.5 0.5 lsb absolute accuracy 6.0 6.0 lsb
276 7.3.5 d/a conversion characteristics table 7.27 d/a conversion characteristics ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item min typ max min typ max unit conditions resolution 8 8 8 8 8 8 bits conversion time 10 10 s 20 pf capacitive load absolute accuracy 2.0 3.0 2.0 3.0 lsb 2 m ? resistive load 2.0 2.0 lsb 4 m ? resistive load
277 7.3.6 flash memory characteristics table 7.28 (a) flash memory characteristics ?preliminary condition a* 7 (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, (program/erase power-supply voltage range: v cc = 3.0 v to 3.6 v), t a = 0? to +75? (program/erase operating temperature range: regular specifications), t a = 0? to +85? (program/erase operating temperature range: wide-range specifications) item symbol min typ max unit test conditions programming time * 1, * 2, * 4 t p tbd 200 ms/ 128 bytes erase time * 1, * 3, * 6 t e tbd 1000 ms/block rewrite times nwec tbd times programming wait time after swe bit setting * 1 x1 s wait time after psu bit setting * 1 y50 s wait time after p bit setting * 1, * 4 z (z1) 30 s1 n 6 (z2) 200 s7 n 1000 (z3) 10 s additional- program- ming time wait wait time after p bit clearing * 1 5 s wait time after psu bit clearing * 1 5 s wait time after pv bit setting * 1 4 s wait time after h'ff dummy write * 1 2 s wait time after pv bit clearing * 1 2 s wait time after swe bit clearing * 1 100 s maximum number of writes * 1, * 4 n 1000 * 5 times erasing wait time after swe bit setting * 1 x1 s wait time after esu bit setting * 1 y 100 s wait time after e bit setting * 1, * 6 z 10 s wait time after e bit clearing * 1 10 s wait time after esu bit clearing * 1 10 s wait time after ev bit setting * 1 20 s wait time after h'ff dummy write * 1 2 s wait time after ev bit clearing * 1 4 s wait time after swe bit clearing * 1 100 s maximum number of erases * 1, * 6 n 100 times
278 notes: 1. follow the program/erase algorithms when making the time settings. 2. programming time per 128 bytes. (indicates the total time during which the p bit is set in flash memory control register 1 (flmcr1). does not include the program-verify time.) 3. time to erase one block. (indicates the time during which the e bit is set in flmcr1. does not include the erase-verify time.) 4. maximum programming time wait time after p bit setting (z) n t p (max) = i=1 5. the maximum number of writes (n) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t p (max)). the wait time after p bit setting (z) should be changed as follows according to the number of writes (n). number of writes (n) 1 n 6 z = 30 s 7 n 1000 z = 200 s [in additional programming] number of writes (n) 1 n 6 z = 10 s 6. for the maximum erase time (t e (max)), the following relationship applies between the wait time after e bit setting (z) and the maximum number of erases (n): t e (max) = wait time after e bit setting (z) maximum number of erases (n) 7. the power-supply voltage range for flash memory programming/erasing is v cc = 3.0 v to 3.6 v.
279 table 7.28 (b) flash memory characteristics ?preliminary condition b: v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, t a = 0? to +75? (program/erase operating temperature range: regular specifications), t a = 0? to +85? (program/erase operating temperature range: wide-range specifications) item symbol min typ max unit test conditions programming time * 1, * 2, * 4 t p 10 200 ms/ 128 bytes erase time * 1, * 3, * 6 t e 50 1000 ms/block rewrite times nwec 100 times programming wait time after swe bit setting * 1 x1 s wait time after psu bit setting * 1 y50 s wait time after p bit setting * 1, * 4 z (z1) 30 s1 n 6 (z2) 200 s7 n 1000 (z3) 10 s additional- program- ming time wait wait time after p bit clearing * 1 5 s wait time after psu bit clearing * 1 5 s wait time after pv bit setting * 1 4 s wait time after h'ff dummy write * 1 2 s wait time after pv bit clearing * 1 2 s wait time after swe bit clearing * 1 100 s maximum number of writes * 1, * 4 n 1000 * 5 times erasing wait time after swe bit setting * 1 x1 s wait time after esu bit setting * 1 y 100 s wait time after e bit setting * 1, * 6 z 10 s wait time after e bit clearing * 1 10 s wait time after esu bit clearing * 1 10 s wait time after ev bit setting * 1 20 s wait time after h'ff dummy write * 1 2 s wait time after ev bit clearing * 1 4 s wait time after swe bit clearing * 1 100 s maximum number of erases * 1, * 6 n 100 times notes: 1. follow the program/erase algorithms when making the time settings. 2. programming time per 128 bytes. (indicates the total time during which the p bit is set in flash memory control register 1 (flmcr1). does not include the program-verify time.) 3. time to erase one block. (indicates the time during which the e bit is set in flmcr1. does not include the erase-verify time.)
280 4. maximum programming time wait time after p bit setting (z) n t p (max) = i=1 5. the maximum number of writes (n) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t p (max)). the wait time after p bit setting (z) should be changed as follows according to the number of writes (n). number of writes (n) 1 n 6 z = 30 s 7 n 1000 z = 200 s [in additional programming] number of writes (n) 1 n 6 z = 10 s 6. for the maximum erase time (t e (max)), the following relationship applies between the wait time after e bit setting (z) and the maximum number of erases (n): t e (max) = wait time after e bit setting (z) maximum number of erases (n) 7. the power-supply voltage range for flash memory programming/erasing is v cc = 3.0 v to 3.6 v.
281 7.4 electrical characteristics of f-ztat version (h8s/2315) (under development) 7.4.1 absolute maximum ratings table 7.29 absolute maximum ratings ?preliminary item symbol value unit power supply voltage v cc 0.3 to +4.3 v input voltage (fwe) v in 0.3 to v cc +0.3 v input voltage (except port 4) v in 0.3 to v cc +0.3 v input voltage (port 4) v in 0.3 to av cc +0.3 v reference power supply voltage v r e f 0.3 to av cc +0.3 v analog power supply voltage av cc 0.3 to +4.3 v analog input voltage v an 0.3 to av cc +0.3 v operating temperature t opr regular specifications: 20 to +75 * c wide-range specifications: 40 to +85 * c storage temperature t stg 55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. note: * the operating temperature ranges for flash memory programming/erasing are as follows: t a = 0 c to +tbd c (regular specifications), t a = 0 c to +tbd c (wide-range specifications). the power-supply voltage range for flash memory programming/erasing is v cc = 3.0 v to 3.6 v.
282 7.4.2 dc characteristics table 7.30 (a) dc characteristics ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage ports 1, 2, irq0 to irq7 vt v cc 0.2 v vt + v cc 0.7 v vt + vt v cc 0.07 v input high voltage res , stby , nmi, md2 to md0, fwe v ih v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v ports 3, a to g 2.2 v cc + 0.3 v port 4 2.2 av cc + 0.3 v input low voltage res , stby , md2 to md0, fwe v il 0.3 v cc 0.1 v nmi, extal, ports 3, 4, a to g 0.3 v cc 0.2 v output high all output pins v oh v cc 0.5 vi oh = 200 a voltage v cc 1.0 vi oh = 1 ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma input leakage res | i in | 10.0 av in = 0.5 to v cc 0.5 v current stby , nmi, md2 to md0, fwe 1.0 a port 4 1.0 av in = 0.5 to av cc 0.5 v three-state leakage current (off state) ports 1, 2, 3, a to g | i tsi | 1.0 av in = 0.5 to v cc 0.5 v
283 item symbol min typ max unit test conditions input pull-up mos current ports a to e i p 10 300 av cc = 2.7 v to 3.6 v, v in = 0 v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25 c current normal operation i cc * 4 tbd (3.0 v) tbd ma f = 20 mhz dissipation * 2 sleep mode tbd (3.0 v) tbd ma f = 20 mhz standby mode * 3 0.01 10 at a 50 c 80 50 c < t a analog power during a/d and d/a conversion ai cc 0.2 (3.0 v) 2.0 ma supply voltage idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 3.0 ma supply voltage idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open . connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. current dissipation values are for v ih min = v cc 0.2 v and v il max = 0.2 v with all output pins unloaded and all mos input pull-ups in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (sleep mode)
284 table 7.30 (b) dc characteristics ?preliminary condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v* 1 , t a = ?0? to +75? (regular specifications), t a = ?0? to +85? (wide-range specifications) item symbol min typ max unit test conditions schmitt trigger input voltage ports 1, 2, irq0 to irq7 vt v cc 0.2 v vt + v cc 0.7 v vt + vt v cc 0.07 v input high voltage res , stby , nmi, md2 to md0, fwe v ih v cc 0.9 v cc + 0.3 v extal v cc 0.7 v cc + 0.3 v ports 3, a to g 2.2 v cc + 0.3 v port 4 2.2 av cc + 0.3 v input low voltage res , stby , md2 to md0, fwe v il 0.3 v cc 0.1 v nmi, extal, ports 3, 4, a to g 0.3 v cc 0.2 v output high all output pins v oh v cc 0.5 vi oh = 200 a voltage v cc 1.0 vi oh = 1 ma output low voltage all output pins v ol 0.4 v i ol = 1.6 ma input leakage res | i in | 10.0 av in = 0.5 to v cc 0.5 v current stby , nmi, md2 to md0, fwe 1.0 a port 4 1.0 av in = 0.5 to av cc 0.5 v three-state leakage current (off state) ports 1, 2, 3, a to g | i tsi | 1.0 av in = 0.5 to v cc 0.5 v
285 item symbol min typ max unit test conditions input pull-up mos current ports a to e i p 10 300 av cc = 3.0 v to 3.6 v, v in = 0 v input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25 c current normal operation i cc * 4 tbd (3.3 v) tbd ma f = 25 mhz dissipation * 2 sleep mode tbd (3.3 v) tbd ma f = 25 mhz standby mode * 3 0.01 10 at a 50 c 80 50 c < t a analog power during a/d and d/a conversion ai cc 0.2 (3.0 v) 2.0 ma supply voltage idle 0.01 5.0 a reference power during a/d and d/a conversion ai cc 1.4 (3.0 v) 3.0 ma supply voltage idle 0.01 5.0 a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open . connect the av cc and v ref pins to v cc , and the av ss pin to v ss . 2. current dissipation values are for v ih min = v cc 0.2 v and v il max = 0.2 v with all output pins unloaded and all mos input pull-ups in the off state. 3. the values are for v ram v cc < 3.0 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + tbd (ma/(mhz v)) v cc f (sleep mode)
286 table 7.31 (a) permissible output currents ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80 ma permissible output high current (per pin) all output pins i oh 2.0 ma permissible output high current (total) total of all output pins i oh 40 ma note: to protect chip reliability, do not exceed the output current values in table 7.31 (a). table 7.31 (b) permissible output currents ?preliminary condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) all output pins i ol 2.0 ma permissible output low current (total) total of all output pins i ol 80 ma permissible output high current (per pin) all output pins i oh 2.0 ma permissible output high current (total) total of all output pins i oh 40 ma note: to protect chip reliability, do not exceed the output current values in table 7.31 (b).
287 7.4.3 ac characteristics (1) clock timing table 7.32 clock timing ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions clock cycle time t cyc 50 500 40 500 ns figure 7.2 clock pulse high width t ch 20 15 ns clock pulse low width t cl 20 15 ns clock rise time t cr 5 5ns clock fall time t cf 5 5ns reset oscillation stabilization time (crystal) t osc1 10 10 ms figure 7.3 software standby oscillation stabilization time (crystal) t osc2 10 10 ms external clock output stabilization delay time t dext 500 500 s figure 7.3
288 (2) control signal timing table 7.33 control signal timing ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions res setup time t ress 200 200 ns figure 7.4 res pulse width t resw 20 20 t cyc nmi setup time t nmis 150 150 ns figure 7.5 nmi hold time t nmih 10 10 nmi pulse width (in recovery from software standby mode) t nmiw 200 200 irq setup time t irqs 150 150 ns irq hold time t irqh 10 10 irq pulse width (in recovery from software standby mode) t irqw 200 200
289 (3) bus timing table 7.34 bus timing ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b item symbol min max min max unit test conditions address delay time t ad 20 20 ns figures 7.6 to 7.10 address setup time t as 0.5 t cyc 15 0.5 t cyc 15 ns address hold time t ah 0.5 t cyc 10 0.5 t cyc 8 ns cs delay time 1 t csd1 20 15 ns as delay time t asd 20 15 ns rd delay time 1 t rsd1 20 15 ns rd delay time 2 t rsd2 20 15 ns read data setup time t rds 15 15 ns read data hold time t rdh 0 0 ns read data access time 1 t acc1 1.0 t cyc 25 1.0 t cyc 20 ns read data access time 2 t acc2 1.5 t cyc 25 1.5 t cyc 20 ns read data access time 3 t acc3 2.0 t cyc 25 2.0 t cyc 20 ns read data access time 4 t acc4 2.5 t cyc 25 2.5 t cyc 20 ns read data access time 5 t acc5 3.0 t cyc 25 3.0 t cyc 20 ns
290 condition a condition b item symbol min max min max unit test conditions wr delay time 1 t wrd1 20 15 ns figures 7.6 to 7.10 wr delay time 2 t wrd2 20 15 ns wr pulse width 1 t wsw1 1.0 t cyc 20 1.0 t cyc 15 ns wr pulse width 2 t wsw2 1.5 t cyc 20 1.5 t cyc 15 ns write data delay time t wdd 30 20 ns write data setup time t wds 0.5 t cyc 20 0.5 t cyc 15 ns write data hold time t wdh 0.5 t cyc 10 0.5 t cyc 8 ns wait setup time t wts 30 25 ns figure 7.8 wait hold time t wth 5 5 ns breq setup time t brqs 30 30 ns figure 7.11 back delay time t bacd 15 15 ns bus floating time t bzd 50 40 ns breqo delay time t brqod 30 25 ns figure 7.12
291 (4) timing of on-chip supporting modules table 7.35 timing of on-chip supporting modules ?reliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item symbol min max min max unit conditions i/o ports output data delay time t pwd 50 40 ns figure 7.13 input data setup time t prs 30 25 input data hold time t prh 30 25 tpu timer output delay time t tocd 50 40 ns figure 7.14 timer input setup time t tics 30 25 timer clock input setup time t tcks 30 25 ns figure 7.15 timer clock pulse width single-edge specification t tckwh 1.5 1.5 t cyc both-edge specification t tckwl 2.5 2.5 8-bit timer timer output delay time t tmod 50 40 ns figure 7.16 timer reset input setup time t tmrs 30 25 ns figure 7.18 timer clock input setup time t tmcs 30 25 ns figure 7.17 timer clock pulse width single-edge specification t tmcwh 1.5 1.5 t cyc both-edge specification t tmcwl 2.5 2.5
292 condition a condition b test item symbol min max min max unit conditions sci input clock asynchronous t scyc 4 4 t cyc figure 7.20 cycle synchronous 6 6 input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 transmit data delay time t txd 50 40 ns figure 7.21 receive data setup time (synchronous) t rxs 50 40 ns receive data hold time (synchronous) t rxh 50 40 ns a/d converter trigger input setup time t trgs 30 30 ns figure 7.22
293 7.4.4 a/d conversion characteristics table 7.36 a/d conversion characteristics ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b item min typ max min typ max unit resolution 10 10 10 10 10 10 bits conversion time 6.7 10.6 s analog input capacitance 20 20 pf permissible signal source impedance 5 5k ? nonlinearity error 5.5 5.5 lsb offset error 5.5 5.5 lsb full-scale error 5.5 5.5 lsb quantization error 0.5 0.5 lsb absolute accuracy 6.0 6.0 lsb
294 7.4.5 d/a conversion characteristics table 7.37 d/a conversion characteristics ?preliminary condition a (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 20 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, ?= 2 mhz to 25 mhz, t a = ?0? to 75? (regular specifications), t a = ?0? to 85? (wide-range specifications) condition a condition b test item min typ max min typ max unit conditions resolution 8 8 8 8 8 8 bits conversion time 10 10 s 20 pf capacitive load absolute accuracy 2.0 3.0 2.0 3.0 lsb 2 m ? resistive load 2.0 2.0 lsb 4 m ? resistive load
295 7.4.6 flash memory characteristics table 7.38 (a) flash memory characteristics ?preliminary condition a* 7 (in planning): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, (program/erase power-supply voltage range: v cc = 3.0 v to 3.6 v), t a = 0? to +75? (program/erase operating temperature range: regular specifications), t a = 0? to +85? (program/erase operating temperature range: wide-range specifications) item symbol min typ max unit test conditions programming time * 1, * 2, * 4 t p tbd 200 ms/ 128 bytes erase time * 1, * 3, * 6 t e tbd 1000 ms/block rewrite times nwec tbd times programming wait time after swe bit setting * 1 x1 s wait time after psu bit setting * 1 y50 s wait time after p bit setting * 1, * 4 z (z1) 30 s1 n 6 (z2) 200 s7 n 1000 (z3) 10 s additional- program- ming time wait wait time after p bit clearing * 1 5 s wait time after psu bit clearing * 1 5 s wait time after pv bit setting * 1 4 s wait time after h'ff dummy write * 1 2 s wait time after pv bit clearing * 1 2 s wait time after swe bit clearing * 1 100 s maximum number of writes * 1, * 4 n 1000 * 5 times erasing wait time after swe bit setting * 1 x1 s wait time after esu bit setting * 1 y 100 s wait time after e bit setting * 1, * 6 z 10 s wait time after e bit clearing * 1 10 s wait time after esu bit clearing * 1 10 s wait time after ev bit setting * 1 20 s wait time after h'ff dummy write * 1 2 s wait time after ev bit clearing * 1 4 s wait time after swe bit clearing * 1 100 s maximum number of erases * 1, * 6 n 100 times
296 notes: 1. follow the program/erase algorithms when making the time settings. 2. programming time per 128 bytes. (indicates the total time during which the p bit is set in flash memory control register 1 (flmcr1). does not include the program-verify time.) 3. time to erase one block. (indicates the time during which the e bit is set in flmcr1. does not include the erase-verify time.) 4. maximum programming time wait time after p bit setting (z) n t p (max) = i=1 5. the maximum number of writes (n) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t p (max)). the wait time after p bit setting (z) should be changed as follows according to the number of writes (n). number of writes (n) 1 n 6 z = 30 s 7 n 1000 z = 200 s [in additional programming] number of writes (n) 1 n 6 z = 10 s 6. for the maximum erase time (t e (max)), the following relationship applies between the wait time after e bit setting (z) and the maximum number of erases (n): t e (max) = wait time after e bit setting (z) maximum number of erases (n) 7. the power-supply voltage range for flash memory programming/erasing is v cc = 3.0 v to 3.6 v.
297 table 7.38 (b) flash memory characteristics ?preliminary condition b (under development): v cc = 3.0 v to 3.6 v, av cc = 3.0 v to 3.6 v, v ref = 3.0 v to av cc , v ss = av ss = 0 v, t a = 0? to +75? (program/erase operating temperature range: regular specifications), t a = 0? to +85? (program/erase operating temperature range: wide- range specifications) item symbol min typ max unit test conditions programming time * 1, * 2, * 4 t p tbd 200 ms/ 128 bytes erase time * 1, * 3, * 6 t e tbd 1000 ms/block rewrite times nwec tbd times programming wait time after swe bit setting * 1 x1 s wait time after psu bit setting * 1 y50 s wait time after p bit setting * 1, * 4 z (z1) 30 s1 n 6 (z2) 200 s7 n 1000 (z3) 10 s additional- program- ming time wait wait time after p bit clearing * 1 5 s wait time after psu bit clearing * 1 5 s wait time after pv bit setting * 1 4 s wait time after h'ff dummy write * 1 2 s wait time after pv bit clearing * 1 2 s wait time after swe bit clearing * 1 100 s maximum number of writes * 1, * 4 n 1000 * 5 times erasing wait time after swe bit setting * 1 x1 s wait time after esu bit setting * 1 y 100 s wait time after e bit setting * 1, * 6 z 10 s wait time after e bit clearing * 1 10 s wait time after esu bit clearing * 1 10 s wait time after ev bit setting * 1 20 s wait time after h'ff dummy write * 1 2 s wait time after ev bit clearing * 1 4 s wait time after swe bit clearing * 1 100 s maximum number of erases * 1, * 6 n 100 times notes: 1. follow the program/erase algorithms when making the time settings. 2. programming time per 128 bytes. (indicates the total time during which the p bit is set in flash memory control register 1 (flmcr1). does not include the program-verify time.)
298 3. time to erase one block. (indicates the time during which the e bit is set in flmcr1. does not include the erase-verify time.) 4. maximum programming time wait time after p bit setting (z) n t p (max) = i=1 5. the maximum number of writes (n) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t p (max)). the wait time after p bit setting (z) should be changed as follows according to the number of writes (n). number of writes (n) 1 n 6 z = 30 s 7 n 1000 z = 200 s [in additional programming] number of writes (n) 1 n 6 z = 10 s 6. for the maximum erase time (t e (max)), the following relationship applies between the wait time after e bit setting (z) and the maximum number of erases (n): t e (max) = wait time after e bit setting (z) maximum number of erases (n) 7. the power-supply voltage range for flash memory programming/erasing is v cc = 3.0 v to 3.6 v. 7.5 usage note although both the f-ztat and mask rom versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip rom, and the layout patterns. if the f-ztat version is used to carry out system evaluation and testing, therefore, when switching to the mask rom version the same evaluation and testing procedures should also be conducted on this version.
299 section 8 registers 8.1 list of registers (address order) address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'f800 mra sm1 sm0 dm1 dm0 md1 md0 dts sz dtc 16/32 * 1 to sar bits h'fbff mrb chne disel chns dar cra crb h'fe80 tcr3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu3 16 bits h'fe81 tmdr3 bfb bfa md3 md2 md1 md0 h'fe82 tior3h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe83 tior3l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'fe84 tier3 ttge tciev tgied tgiec tgieb tgiea h'fe85 tsr3 tcfv tgfd tgfc tgfb tgfa h'fe86 tcnt3 h'fe87 h'fe88 tgr3a h'fe89 h'fe8a tgr3b h'fe8b h'fe8c tgr3c h'fe8d h'fe8e tgr3d h'fe8f
300 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fe90 tcr4 cclr1 cclr0 ckeg ckeg0 tpsc2 tpsc1 tpsc0 tpu4 16 bits h'fe91 tmdr4 md3 md2 md1 md0 h'fe92 tior4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe94 tier4 ttge tcieu tciev tgieb tgiea h'fe95 tsr4 tcfd tcfu tcfv tgfb tgfa h'fe96 tcnt4 h'fe97 h'fe98 tgr4a h'fe99 h'fe9a tgr4b h'fe9b h'fea0 tcr5 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu5 16 bits h'fea1 tmdr5 md3 md2 md1 md0 h'fea2 tior5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fea4 tier5 ttge tcieu tciev tgieb tgiea h'fea5 tsr5 tcfd tcfu tcfv tgfb tgfa h'fea6 tcnt5 h'fea7 h'fea8 tgr5a h'fea9 h'feaa tgr5b h'feab h'feb0 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr ports 8 bits h'feb1 p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr h'feb2 p3ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr h'feb9 paddr pa3ddr pa2ddr pa1ddr pa0ddr h'feba pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr h'febb pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr h'febc pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr h'febd peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr h'febe pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr h'febf pgddr pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr
301 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fec4 ipra ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 interrupt 8 bits h'fec5 iprb ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 controller h'fec6 iprc ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec7 iprd ipr6 ipr5 ipr4 h'fec8 ipre ipr2 ipr1 ipr0 h'fec9 iprf ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'feca iprg ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fecb iprh ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fecc ipri ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fecd iprj ipr2 ipr1 ipr0 h'fece iprk ipr6 ipr5 ipr4 h'fed0 abwcr abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller 8 bits h'fed1 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'fed2 wcrh w71 w70 w61 w60 w51 w50 w41 w40 h'fed3 wcrl w31 w30 w21 w20 w11 w10 w01 w00 h'fed4 bcrh icis1 icis0 brstrm brsts1 brsts0 h'fed5 bcrl brle breqoe eae waite h'fedb ramer * 2 rams ram2 ram1 ram0 flash memory 8 bits h'ff2c iscrh irq7scb irq7sca irq6scb irq6sca irq5scb irq5sca irq4scb irq4sca interrupt 8 bits h'ff2d iscrl irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca controller h'ff2e ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e h'ff2f isr irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f h'ff30 to h'ff34 dtcer dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 dtc 8 bits h'ff37 dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 h'ff38 sbycr ssby sts2 sts1 sts0 ope irq37s power-down mode 8 bits h'ff39 syscr intm1 intm0 nmieg lwrod rame mcu 8 bits h'ff3a sckcr pstop div sck2 sck1 sck0 clock pulse generator 8 bits h'ff3b mdcr mds2 mds1 mds0 mcu 8 bits h'ff3c mstpcrh mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 power-down 8 bits h'ff3d mstpcrl mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 mode
302 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff42 syscr2 * 2 flshe flash memory 8 bits h'ff44 reserved reserved h'ff45 pfcr1 css17 css36 pf1cs5s p f0 cs 4 sa23e a22e a21e a20e ports 8 bits h'ff50 port1 p17 p16 p15 p14 p13 p12 p11 p10 h'ff51 port2 p27 p26 p25 p24 p23 p22 p21 p20 h'ff52 port3 p35 p34 p33 p32 p31 p30 h'ff53 port4 p47 p46 p45 p44 p43 p42 p41 p40 h'ff59 porta pa3 pa2 pa1 pa0 h'ff5a portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'ff5b portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 h'ff5c portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 h'ff5d porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 h'ff5e portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 h'ff5f portg pg4 pg3 pg2 pg1 pg0 h'ff60 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr h'ff61 p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr h'ff62 p3dr p35dr p34dr p33dr p32dr p31dr p30dr h'ff69 padr pa3dr pa2dr pa1dr pa0dr h'ff6a pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr h'ff6b pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr h'ff6c pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr h'ff6d pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr h'ff6e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr h'ff6f pgdr pg4dr pg3dr pg2dr pg1dr pg0dr h'ff70 papcr pa3pcr pa2pcr pa1pcr pa0pcr h'ff71 pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr h'ff72 pcpcr pc7pcrpc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr h'ff73 pdpcr pd7pcrpd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr h'ff74 pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr h'ff76 p3odr p35odr p34odr p33odr p32odr p31odr p30odr h'ff77 paodr pa3odr pa2odr pa1odr pa0odr
303 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff78 smr0 c/ a / gm * 3 chr/ blk * 4 pe o/ e stop/ bcp1 * 5 mp/ bcp0 * 6 cks1 cks0 sci0, smart card 8 bits h'ff79 brr0 interface 0 h'ff7a scr0 tie rie te re mpie teie cke1 cke0 h'ff7b tdr0 h'ff7c ssr0 tdre rdrf orer fer/ ers * 7 per tend mpb mpbt h'ff7d rdr0 h'ff7e scmr0 sdir sinv smif h'ff80 smr1 c/ a / gm * 3 chr/ blk * 4 pe o/ e stop/ bcp1 * 5 mp/ bcp0 * 6 cks1 cks0 sci1, smart card 8 bits h'ff81 brr1 interface 1 h'ff82 scr1 tie rie te re mpie teie cke1 cke0 h'ff83 tdr1 h'ff84 ssr1 tdre rdrf orer fer/ ers * 7 per tend mpb mpbt h'ff85 rdr1 h'ff86 scmr1 sdir sinv smif
304 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fe90 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter 8 bits h'fe91 addral ad1 ad0 h'fe92 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fe93 addrbl ad1 ad0 h'fe94 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fe95 addrcl ad1 ad0 h'fe96 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'fe97 addrdl ad1 ad0 h'fe98 adcsr adf adie adst scan cks ch2 ch1 ch0 h'fe99 adcr trgs1 trgs0 cks1 h'ffa4 dadr0 d/a converter 8 bits h'ffa5 dadr1 h'ffa6 dacr01 daoe1 daoe0 dae h'ffac pfcr2 cs167e cs25e asod ports 8 bits h'ffb0 tcr0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8-bit timer 16 bits h'ffb1 tcr1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 channel 0, 1 h'ffb2 tcsr0 cmfb cmfa ovf adte os3 os2 os1 os0 h'ffb3 tcsr1 cmfb cmfa ovf os3 os2 os1 os0 h'ffb4 tcora0 h'ffb5 tcora1 h'ffb6 tcorb0 h'ffb7 tcorb1 h'ffb8 tcnt0 h'ffb9 tcnt1 h'ffbc (read) tcsr ovf wt/ it tme cks2 cks1 cks0 wdt 16 bits h'ffbd (read) tcnt h'ffbf (read) rstcsr wovf rste
305 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ffc0 tstr cst5 cst4 cst3 cst2 cst1 cst0 tpu 16 bits h'ffc1 tsyr sync5 sync4 sync3 sync2 sync1 sync0 h'ffc8 flmcr1 * 8 fwe swe esu psu ev pv e p flash memory 8 bits h'ffc8 flmcr1 * 9 fwe swe1 esu1 psu1 ev1 pv1 e1 p1 h'ffc9 flmcr2 * 8 fler h'ffc9 flmcr2 * 9 fler swe2 esu2 psu2 ev2 pv2 e2 p2 h'ffca ebr1 * 2 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ffcb ebr2 * 2 eb15 * 9 eb14 * 9 eb13 * 8 eb12 * 8 eb11 eb10 eb9 eb8 h'ffd0 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu0 16 bits h'ffd1 tmdr0 bfb bfa md3 md2 md1 md0 h'ffd2 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffd3 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ffd4 tier0 ttge tciev tgied tgiec tgieb tgiea h'ffd5 tsr0 tcfv tgfd tgfc tgfb tgfa h'ffd6 tcnt0 h'ffd7 h'ffd8 tgr0a h'ffd9 h'ffda tgr0b h'ffdb h'ffdc tgr0c h'ffdd h'ffde tgr0d h'ffdf
306 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ffe0 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu1 16 bits h'ffe1 tmdr1 md3 md2 md1 md0 h'ffe2 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffe4 tier1 ttge tcieu tciev tgieb tgiea h'ffe5 tsr1 tcfd tcfu tcfv tgfb tgfa h'ffe6 tcnt1 h'ffe7 h'ffe8 tgr1a h'ffe9 h'ffea tgr1b h'ffeb h'fff0 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu2 16 bits h'fff1 tmdr2 md3 md2 md1 md0 h'fff2 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fff4 tier2 ttge tcieu tciev tgieb tgiea h'fff5 tsr2 tcfd tcfu tcfv tgfb tgfa h'fff6 tcnt2 h'fff7 h'fff8 tgr2a h'fff9 h'fffa tgr2b h'fffb notes: 1. located in on-chip ram. the bus width is 32 bits when the dtc accesses this area as register information, and 16 bits otherwise. 2. valid only in f-ztat version. 3. functions as c/ a for sci use, and as gm for smart card interface use. 4. functions as chr for sci use, and as blk for smart card interface use. 5. functions as stop for sci use, and as bcp1 for smart card interface use. 6. functions as mp for sci use, and as bcp0 for smart card interface use. 7. functions as fer for sci use, and as ers for smart card interface use. 8. valid in h8s/2319 f-ztat and h8s/2315 f-ztat versions. 9. valid in h8s/2319 f-ztat version only.
307 8.2 list of registers (by module) module register abbreviation r/w initial value address * 1 interrupt system control register syscr r/w h'01 h'ff39 controller irq sense control register h iscrh r/w h'00 h'ff2c irq sense control register l iscrl r/w h'00 h'ff2d irq enable register ier r/w h'00 h'ff2e irq status register isr r/(w) * 2 h'00 h'ff2f interrupt priority register a ipra r/w h'77 h'fec4 interrupt priority register b iprb r/w h'77 h'fec5 interrupt priority register c iprc r/w h'77 h'fec6 interrupt priority register d iprd r/w h'77 h'fec7 interrupt priority register e ipre r/w h'77 h'fec8 interrupt priority register f iprf r/w h'77 h'fec9 interrupt priority register g iprg r/w h'77 h'feca interrupt priority register h iprh r/w h'77 h'fecb interrupt priority register i ipri r/w h'77 h'fecc interrupt priority register j iprj r/w h'77 h'fecd interrupt priority register k iprk r/w h'77 h'fece dtc dtc mode register a mra * 3 undefined * 4 dtc mode register b mrb * 3 undefined * 4 dtc source address register sar * 3 undefined * 4 dtc destination address register dar * 3 undefined * 4 dtc transfer count register a cra * 3 undefined * 4 dtc transfer count register b crb * 3 undefined * 4 dtc enable register dtcer r/w h'00 h'ff30 to h'ff34 dtc vector register dtvecr r/w h'00 h'ff37 module stop control register mstpcr r/w h'3fff h'ff3c
308 module register abbreviation r/w initial value address * 1 bus bus width control register abwcr r/w h'ff/h'00 * 5 h'fed0 controller access state control register astcr r/w h'ff h'fed1 wait control register h wcrh r/w h'ff h'fed2 wait control register l wcrl r/w h'ff h'fed3 bus control register h bcrh r/w h'd0 h'fed4 bus control register l bcrl r/w h'3c h'fed5 8-bit timer control register 0 tcr0 r/w h'00 h'ffb0 timer 0 timer control/status register 0 tcsr0 r/(w) * 7 h'00 h'ffb2 timer constant register a0 tcora0 r/w h'ff h'ffb4 timer constant register b0 tcorb0 r/w h'ff h'ffb6 timer counter 0 tcnt0 r/w h'00 h'ffb8 8-bit timer control register 1 tcr1 r/w h'00 h'ffb1 timer 1 timer control/status register 1 tcsr1 r/(w) * 7 h'10 h'ffb3 timer constant register a1 tcora1 r/w h'ff h'ffb5 timer constant register b1 tcorb1 r/w h'ff h'ffb7 timer counter 1 tcnt1 r/w h'00 h'ffb9 all 8-bit timer channels module stop control register mstpcr r/w h'3fff h'ff3c wdt timer control/status register tcsr r/(w) * 9 h'18 h'ffbc: write * 8 h'ffbc: read timer counter tcnt r/w h'00 h'ffbc: write * 6 h'ffbd: read reset control/status register rstcsr r/(w) * 9 h'1f h'ffbe: write * 8 h'ffbf: read
309 module register abbreviation r/w initial value address * 1 sci0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e sci1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 all sci channels module stop control register mstpcr r/w h'3fff h'ff3c smci0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e smci1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86
310 module register abbreviation r/w initial value address * 1 all smci channels module stop control register mstpcr r/w h'3fff h'ff3c adc a/d data register ah addrah r h'00 h'ff90 a/d data register al addral r h'00 h'ff91 a/d data register bh addrbh r h'00 h'ff92 a/d data register bl addrbl r h'00 h'ff93 a/d data register ch addrch r h'00 h'ff94 a/d data register cl addrcl r h'00 h'ff95 a/d data register dh addrdh r h'00 h'ff96 a/d data register dl addrdl r h'00 h'ff97 a/d control/status register adcsr r/(w) * 9 h'00 h'ff98 a/d control register adcr r/w h'3f h'ff99 module stop control register mstpcr r/w h'3fff h'ff3c dac0, 1 d/a data register 0 dadr0 r/w h'00 h'ffa4 d/a data register 1 dadr1 r/w h'00 h'ffa5 d/a control register 01 dacr01 r/w h'1f h'ffa6 all dac channels module stop control register mstpcr r/w h'3fff h'ff3c on-chip ram system control register syscr r/w h'01 h'ff39 tpu0 timer control register 0 tcr0 r/w h'00 h'ffd0 timer mode register 0 tmdr0 r/w h'c0 h'ffd1 timer i/o control register 0h tior0h r/w h'00 h'ffd2 timer i/o control register 0l tior0l r/w h'00 h'ffd3 timer interrupt enable register 0 tier0 r/w h'40 h'ffd4 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ffd5 timer counter 0 tcnt0 r/w h'0000 h'ffd6 timer general register 0a tgr0a r/w h'ffff h'ffd8 timer general register 0b tgr0b r/w h'ffff h'ffda timer general register 0c tgr0c r/w h'ffff h'ffdc timer general register 0d tgr0d r/w h'ffff h'ffde tpu1 timer control register 1 tcr1 r/w h'00 h'ffe0 timer mode register 1 tmdr1 r/w h'c0 h'ffe1
311 module register abbreviation r/w initial value address * 1 tpu1 timer i/o control register 1 tior1 r/w h'00 h'ffe2 timer interrupt enable register 1 tier1 r/w h'40 h'ffe4 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ffe5 timer counter 1 tcnt1 r/w h'0000 h'ffe6 timer general register 1a tgr1a r/w h'ffff h'ffe8 timer general register 1b tgr1b r/w h'ffff h'ffea tpu2 timer control register 2 tcr2 r/w h'00 h'fff0 timer mode register 2 tmdr2 r/w h'c0 h'fff1 timer i/o control register 2 tior2 r/w h'00 h'fff2 timer interrupt enable register 2 tier2 r/w h'40 h'fff4 timer status register 2 tsr2 r/(w) * 2 h'c0 h'fff5 timer counter 2 tcnt2 r/w h'0000 h'fff6 timer general register 2a tgr2a r/w h'ffff h'fff8 timer general register 2b tgr2b r/w h'ffff h'fffa tpu3 timer control register 3 tcr3 r/w h'00 h'fe80 timer mode register 3 tmdr3 r/w h'c0 h'fe81 timer i/o control register 3h tior3h r/w h'00 h'fe82 timer i/o control register 3l tior3l r/w h'00 h'fe83 timer interrupt enable register 3 tier3 r/w h'40 h'fe84 timer status register 3 tsr3 r/(w) * 2 h'c0 h'fe85 timer counter 3 tcnt3 r/w h'0000 h'fe86 timer general register 3a tgr3a r/w h'ffff h'fe88 timer general register 3b tgr3b r/w h'ffff h'fe8a timer general register 3c tgr3c r/w h'ffff h'fe8c timer general register 3d tgr3d r/w h'ffff h'fe8e tpu4 timer control register 4 tcr4 r/w h'00 h'fe90 timer mode register 4 tmdr4 r/w h'c0 h'fe91 timer i/o control register 4 tior4 r/w h'00 h'fe92 timer interrupt enable register 4 tier4 r/w h'40 h'fe94 timer status register 4 tsr4 r/(w) * 2 h'c0 h'fe95 timer counter 4 tcnt4 r/w h'0000 h'fe96 timer general register 4a tgr4a r/w h'ffff h'fe98 timer general register 4b tgr4b r/w h'ffff h'fe9a
312 module register abbreviation r/w initial value address * 1 tpu5 timer control register 5 tcr5 r/w h'00 h'fea0 timer mode register 5 tmdr5 r/w h'c0 h'fea1 timer i/o control register 5 tior5 r/w h'00 h'fea2 timer interrupt enable register 5 tier5 r/w h'40 h'fea4 timer status register 5 tsr5 r/(w) * 2 h'c0 h'fea5 timer counter 5 tcnt5 r/w h'0000 h'fea6 timer general register 5a tgr5a r/w h'ffff h'fea8 timer general register 5b tgr5b r/w h'ffff h'feaa all tpu timer start register tstr r/w h'00 h'ffc0 channels timer synchro register tsyr r/w h'00 h'ffc1 module stop control register mstpcr r/w h'3fff h'ff3c flash flash memory control register 1 flmcr1 * 14 r/w * 11 h'00/h'80 * 12 h'ffc8 * 10 memory flash memory control register 2 flmcr2 * 14 r/w * 11 h'00 h'ffc9 * 10 erase block register 1 ebr1 * 14 r/w * 11 h'00 * 13 h'ffca * 10 erase block register 2 ebr2 * 14 r/w * 11 h'00 * 13 h'ffcb * 10 ram emulation register ramer r/w h'00 h'fedb system control register 2 syscr2 * 15 r/w h'00 h'ff42 clock pulse generator system clock control register sckcr r/w h'00 h'ff3a mcu system control register syscr r/w h'01 h'ff39 mode control register mdcr r undefined h'ff3b power- standby control register sbycr r/w h'08 h'ff38 down state module stop control register h mstpcrh r/w h'3f h'ff3c module stop control register l mstpcrl r/w h'ff h'ff3d port 1 port 1 data direction register p1ddr w h'00 h'feb0 port 1 data register p1dr r/w h'00 h'ff60 port 1 register port1 r undefined h'ff50 port function control register 1 pfcr1 r/w h'0f h'ff45 port 2 port 2 data direction register p2ddr w h'00 h'feb1 port 2 data register p2dr r/w h'00 h'ff61 port 2 register port2 r undefined h'ff51
313 module register abbreviation r/w initial value address * 1 port 3 port 3 data direction register p3ddr w h'00 h'feb2 port 3 data register p3dr r/w h'00 h'ff62 port 3 register port3 r undefined h'ff52 port 3 open drain control register p3odr r/w h'00 h'ff76 port 4 port 4 register port4 r undefined h'ff53 port a port a data direction register paddr w h'0 * 16 h'feb9 port a data register padr r/w h'0 * 16 h'ff69 port a register porta r undefined * 16 h'ff59 port a mos pull-up control register papcr r/w h'0 * 16 h'ff70 port a open drain control register paodr r/w h'0 * 16 h'ff77 port b port b data direction register pbddr w h'00 h'feba port b data register pbdr r/w h'00 h'ff6a port b register portb r undefined h'ff5a port b mos pull-up control register pbpcr r/w h'00 h'ff71 port c port c data direction register pcddr w h'00 h'febb port c data register pcdr r/w h'00 h'ff6b port c register portc r undefined h'ff5b port c mos pull-up control register pcpcr r/w h'00 h'ff72 port d port d data direction register pdddr w h'00 h'febc port d data register pddr r/w h'00 h'ff6c port d register portd r undefined h'ff5c port d mos pull-up control register pdpcr r/w h'00 h'ff73 port e port e data direction register peddr w h'00 h'febd port e data register pedr r/w h'00 h'ff6d port e register porte r undefined h'ff5d port e mos pull-up control register pepcr r/w h'00 h'ff74 port f port f data direction register pfddr w h'80/h'00 * 17 h'febe port f data register pfdr r/w h'00 h'ff6e port f register portf r undefined h'ff5e port function control register 1 pfcr1 r/w h'0f h'ff45 port function control register 2 pfcr2 r/w h'30 h'ffac system control register syscr r/w h'01 h'ff39
314 module register abbreviation r/w initial value address * 1 port g port g data direction register pgddr w h'10/h'00 * 17 * 18 h'febf port g data register pgdr r/w h'00 * 18 h'ff6f port g register portg r undefined * 18 h'ff5f port function control register 1 pfcr1 r/w h'0f h'ff45 port function control register 2 pfcr2 r/w h'30 h'ffac notes: 1. lower 16 bits of the address. 2. only 0 can be written for flag clearing. 3. registers in the dtc cannot be read or written to directly. 4. located as register information in on-chip ram addresses h'ebc0 to h'efbf. cannot be located in external memory space. do not clear the rame bit in syscr to 0 when using the dtc. 5. determined by the mcu operating mode. 6. bits used for pulse output cannot be written to. 7. only 0 can be written to bits 7 to 5, to clear the flags. 8. for information on writing, see section 10.2.4, notes on register access, in the hardware manual. 9. only 0 can be written to bit 7, to clear the flag. 10. flash memory registers selection is performed by means of the flshe bit in system control register 2 (syscr2). 11. in modes in which the on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes are also disabled when the fwe bit in flmcr1 is cleared to 0. (except for h8s/2319 f-ztat) 12. in h8s/2318 f-ztat and h8s/2315 f-ztat, when a high level is input to the fwe pin, the initial value is h'80. in h8s/2319 f-ztat, the initial value is h'80. 13. in h8s/2318 f-ztat and h8s/2315 f-ztat, when a low level is input to the fwe pin, or if a high level is input but the swe bit in flmcr1 is not set, these registers are initialized to h'00. in the h8s/2319 f-ztat, the eb11 to eb0 bits are initialized to 0 when the swe1 bit is not set to 1, and the eb15 to eb12 bits are initialized to 0 when the swe2 bit is not set to 1. 14. flmcr1, flmcr2, ebr1, and ebr2 are 8-bit registers. only byte access can be used on these registers, with the access requiring two states. 15. the syscr2 register can only be used in the f-ztat version. in the mask rom version this register will return an undefined value if read, and cannot be written to. 16. value of bits 3 to 0. 17. the initial value depends on the mode. 18. value of bits 4 to 0.
315 8.3 functions mra?tc mode register a h'f800?'fbff dtc 7 sm1 undefined 6 sm0 undefined 5 dm1 undefined 4 dm0 undefined 3 md1 undefined 0 sz undefined 2 md0 undefined 1 dts undefined bit initial value read/write : : : 0 1 source address mode 0 1 0 1 destination address mode 0 1 dtc mode 0 1 normal mode repeat mode block transfer mode 0 1 0 1 dtc data transfer size 0 1 byte-size transfer dtc transfer mode select 0 1 word-size transfer destination side is repeat area or block area source side is repeat area or block area dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) dar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1) dar is fixed sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) sar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1) sar is fixed
316 mrb?tc mode register b h'f800?'fbff dtc 0 1 after dtc data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 after dtc data transfer ends, the cpu interrupt is enabled 7 chne undefined 6 disel undefined 5 chns undefined 4 undefined 3 undefined 0 undefined 2 undefined 1 undefined bit initial value read/write : : : dtc chain transfer enable dtc chain transfer select chne 0 1 1 chns 0 1 description no chain transfer. (at end of dtc data transfer, dtc waits for activation) chain transfer every time chain transfer only when transfer counter = 0 dtc interrupt select reserved only 0 should be written to these bits sar?tc source address register h'f800?'fbff dtc 23 bit initial value read/write : : : 22 21 20 19 43210 - - - - - - - - - - - - specifies dtc transfer data source address unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined
317 dar?tc destination address register h'f800?'fbff dtc 23 bit initial value read/write : : : 22 21 20 19 43210 - - - - - - - - - - - - specifies dtc transfer data destination address unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined cra?tc transfer count register a h'f800?'fbff dtc 15 bit initial value read/write : : : 14 13 12 11109876543210 crah cral specifies the number of dtc data transfers unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined crb?tc transfer count register b h'f800?'fbff dtc 15 14 13 12 11109876543210 specifies the number of dtc block data transfers bit initial value read/write : : : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined
318 tcr3?imer control register 3 h'fe80 tpu3 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write : : : tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 counter clear 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input internal clock: counts on /1024 internal clock: counts on /256 internal clock: counts on /4096 timer prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 notes: 1. 2. synchronous operation setting is performed by setting the sync bit in tsyr to 1. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. note: the internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if /1 or overflow/underflow on another channel is selected as the input clock.
319 tmdr3?imer mode register 3 h'fe81 tpu3 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : : 0 buffer operation b tgrb operates normally 0 buffer operation a tgra operates normally 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: 1. 2. * : don't care md3 is a reserved bit. in a write, it should always be written with 0. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. tgra and tgrc used together for buffer operation 1 tgrb and tgrd used together for buffer operation 1
320 tior3h?imer i/o control register 3h h'fe82 tpu3 0 1 tgr3b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr3a is output compare register tgr3a i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges * : don't care * : don't care 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write : : : tgr3a is input capture register initial output is 0 output output disabled initial output is 1 output capture input source is tioca3 pin capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down tgr3b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr3b is input capture register initial output is 0 output output disabled initial output is 1 output capture input source is tiocb3 pin capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down * 1 note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000, and /1 is used as the tcnt4 count clock, this setting is invalid and input capture does not occur.
321 tior3l?imer i/o control register 3l h'fe83 tpu3 0 1 tgr3d i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr3c is output compare register * 1 tgr3c i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don't care * : don't care notes: note: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare does not occur. note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w bit initial value read/write : : : initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tiocc3 pin tgr3c is input capture register * 1 capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down tgr3d is output compare register * 2 output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tiocd3 pin tgr3d is input capture register * 2 capture input source is channel 4/count clock input capture at tcnt4 count-up/ count-down * 1 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture does not occur. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare does not occur.
322 tier3?imer interrupt enable register 3 h'fe84 tpu3 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value read/write : : : 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable tgr interrupt enable d tgr interrupt enable c tgr interrupt enable b 0 1 interrupt request (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 0 1 0 1 interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled interrupt request (tgic) by tgfc bit disabled interrupt request (tgic) by tgfc bit enabled interrupt request (tgid) by tgfd bit disabled interrupt request (tgid) by tgfd bit enabled
323 tsr3?imer status register 3 h'fe85 tpu3 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value read/write : : : note: * can only be written with 0 for flag clearing. 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 overflow flag 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) 0 [clearing conditions] when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfd after reading tgfd = 1 input capture/output compare flag d 1 [setting conditions] 0 [clearing conditions] when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfc after reading tgfc = 1 input capture/output compare flag c 1 [setting conditions] 0 [clearing conditions] when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 input capture/output compare flag b 1 [setting conditions] 0 [clearing conditions] when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 [setting conditions] when tcnt=tgra while tgra is function- ing as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register when tcnt = tgrc while tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register when tcnt = tgrd while tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register
324 tcnt3?imer counter 3 h'fe86 tpu3 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter tgr3a?imer general register 3a h'fe88 tpu3 tgr3b?imer general register 3b h'fe8a tpu3 tgr3c?imer general register 3c h'fe8c tpu3 tgr3d?imer general register 3d h'fe8e tpu3 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
325 tcr4?imer control register 4 h'fe90 tpu4 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on /1024 counts on tcnt5 overflow/underflow timer prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write : : : note: this setting is ignored when channel 4 is in phase counting mode. note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. note: this setting is ignored when channel 4 is in phase counting mode. the internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if /1 or overflow/underflow on another channel is selected as the input clock. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *
326 tmdr4?imer mode register 4 h'fe91 tpu4 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * note: * : don't care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : : md3 is a reserved bit. in a write, it should always be written with 0.
327 tior4?imer i/o control register 4 h'fe92 tpu4 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write : : : 0 1 tgr4b is output compare register tgr4b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * tgr4a i/o control * : don't care 0 1 tgr4a is output compare register 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don't care initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges tgr4a is input capture register capture input source is tioca4 pin input capture at generation of tgr3a compare match/input capture capture input source is tgr3a compare match/ input capture output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges tgr4b is input capture register capture input source is tiocb4 pin input capture at generation of tgr3c compare match/input capture capture input source is tgr3c compare match/ input capture
328 tier4?imer interrupt enable register 4 h'fe94 tpu4 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value read/write : : : 0 1 0 1 0 1 interrupt request (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 0 1 interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled tgr interrupt enable b interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable underflow interrupt enable interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled a/d conversion start request enable a/d conversion start request generation disabled a/d conversion start request generation enabled
329 tsr4?imer status register 4 h'fe95 tpu4 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value read/write : : : 0 1 tcnt counts down tcnt counts up count direction flag 0 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 underflow flag 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) 0 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 overflow flag 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000) 0 input capture/output compare flag b 1 0 [clearing conditions] when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 [setting conditions] note: * can only be written with 0 for flag clearing. when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing conditions] when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register
330 tcnt4?imer counter 4 h'fe96 tpu4 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. up/down-counter * tgr4a?imer general register 4a h'fe98 tpu4 tgr4b?imer general register 4b h'fe9a tpu4 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
331 tcr5?imer control register 5 h'fea0 tpu5 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on /256 external clock: counts on tclkd pin input time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value read/write : : : note: 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges this setting is ignored when channel 5 is in phase counting mode. note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. note: this setting is ignored when channel 5 is in phase counting mode. the internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if /1 or overflow/underflow on another channel is selected as the input clock. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *
332 tmdr5?imer mode register 5 h'fea1 tpu5 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * note: md3 is a reserved bit. in a write, it should always be written with 0. * : don't care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : :
333 tior5?imer i/o control register 5 h'fea2 tpu5 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value read/write : : : 0 1 tgr5b i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 tgr5a is output compare register tgr5a i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don't care tgr5a is input capture register initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tioca5 pin tgr5b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match * : don't care tgr5b is input capture register initial output is 0 output output disabled 0 output at compare match 1 output at compare match toggle output at compare match initial output is 1 output input capture at rising edge input capture at falling edge input capture at both edges capture input source is tiocb5 pin
334 tier5?imer interrupt enable register 5 h'fea4 tpu5 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value read/write : : : 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled underflow interrupt enable tgr interrupt enable b 0 1 interrupt request (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 0 1 overflow interrupt enable interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit disabled interrupt request (tgib) by tgfb bit enabled interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled
335 tsr5?imer status register 5 h'fea5 tpu5 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value read/write : : : 0 1 tcnt counts down tcnt counts up count direction flag 0 underflow flag 1 0 overflow flag 1 0 input capture/output compare flag b 1 0 [clearing conditions] when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register note: * can only be written with 0 for flag clearing. [clearing conditions] when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff)
336 tcnt5?imer counter 5 h'fea6 tpu5 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. up/down-counter * tgr5a?imer general register 5a h'fea8 tpu5 tgr5b?imer general register 5b h'feaa tpu5 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w p1ddr?ort 1 data direction register h'feb0 port 1 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value read/write : : : specify input or output for individual port 1 pins
337 p2ddr?ort 2 data direction register h'feb1 port 2 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 0 p20ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w specify input or output for individual port 2 pins bit initial value read/write : : : p3ddr?ort 3 data direction register h'feb2 port 3 7 undefined 6 undefined 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w specify input or output for individual port 3 pins bit initial value read/write : : : paddr?ort a data direction register h'feb9 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value read/write : : : specify input or output for individual port a pins
338 pbddr?ort b data direction register h'feba port b 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w specify input or output for individual port b pins bit initial value read/write : : : pcddr?ort c data direction register h'febb port c 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w specify input or output for individual port c pins bit initial value read/write : : : pdddr?ort d data direction register h'febc port d 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value read/write : : : specify input or output for individual port d pins peddr?ort e data direction register h'febd port e 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w specify input or output for individual port e pins bit initial value read/write : : :
339 pfddr?ort f data direction register h'febe port f 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w specify input or output for individual port f pins bit modes 4 to 6 * initial value read/write mode 7 * initial value read/write : : : : : note: * modes 6 and 7 cannot be used in the romless version. pgddr?ort g data direction register h'febf port g 7 undefined undefined 6 undefined undefined 5 undefined undefined 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w specify input or output for individual port g pins note: * modes 6 and 7 cannot be used in the romless version. bit modes 4 and 5 initial value read/write modes 6 and 7 initial value read/write : : : * : :
340 ipra interrupt priority register a h'fec4 interrupt controller iprb interrupt priority register b h'fec5 interrupt controller iprc interrupt priority register c h'fec6 interrupt controller iprd interrupt priority register d h'fec7 interrupt controller ipre interrupt priority register e h'fec8 interrupt controller iprf interrupt priority register f h'fec9 interrupt controller iprg interrupt priority register g h'feca interrupt controller iprh interrupt priority register h h'fecb interrupt controller ipri interrupt priority register i h'fecc interrupt controller iprj interrupt priority register j h'fecd interrupt controller iprk interrupt priority register k h'fece interrupt controller 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w set priority (levels 7 to 0) for interrupt sources ipra iprb iprc iprd ipre iprf iprg iprh ipri iprj iprk register bits irq0 irq2 irq3 irq6 irq7 wdt * tpu channel 0 tpu channel 2 tpu channel 4 8-bit timer channel 0 * sci channel 1 irq1 irq4 irq5 dtc * a/d converter tpu channel 1 tpu channel 3 tpu channel 5 8-bit timer channel 1 sci channel 0 * 6 to 4 2 to 0 correspondence between interrupt sources and ipr settings note: * reserved bits. bit initial value read/write : : :
341 abwcr?us width control register h'fed0 bus controller 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit modes 5 to 7 * initial value r/w mode 4 initial value read/write : : : : : area 7 to 0 bus width control note: * modes 6 and 7 cannot be used in the romless version. 0 1 area n is designated for 16-bit access area n is designated for 8-bit access (n = 7 to 0) astcr?ccess state control register h'fed1 bus controller 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value read/write : : : area 7 to 0 access state control 0 1 area n is designated for 2-state access wait state insertion in area n external space is disabled area n is designated for 3-state access wait state insertion in area n external space is enabled (n = 7 to 0)
342 wcrh?ait control register h h'fed2 bus controller 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value read/write : : : area 7 wait control area 6 wait control area 5 wait control area 4 wait control 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
343 wcrl?ait control register l h'fed3 bus controller 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value read/write : : : area 3 wait control area 2 wait control area 1 wait control area 0 wait control 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
344 bcrh?us control register h h'fed4 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write : : : idle cycle insert 1 0 1 idle cycle not inserted in case of successive external read cycles in different areas idle cycle inserted in case of successive external read cycles in different areas idle cycle insert 0 0 1 idle cycle not inserted in case of successive external read and external write cycles idle cycle inserted in case of successive external read and external write cycles area 0 burst rom enable 0 1 basic bus interface burst rom interface burst cycle select 1 0 1 burst cycle comprises 1 state burst cycle comprises 2 states burst cycle select 0 0 1 max. 4 words in burst access max. 8 words in burst access reserved only 0 should be written to these bits
345 bcrl?us control register l h'fed5 bus controller 7 brle 0 r/w 6 breqoe 0 r/w 5 eae 1 r/w 4 1 r/w 3 1 r/w 0 waite 0 r/w 2 1 r/w 1 0 r/w bit initial value read/write : : : bus release enable 0 1 external bus release disabled external bus release enabled breqo pin enable 0 1 breqo output disabled breqo output enabled 0 1 addresses h'010000 to h'03ffff * 2 : h8s/2319 and h8s/2315: on-chip rom h8s/2318: on-chip rom h8s/2317: on-chip rom at addresses h'010000 to h'01ffff and reserved area * 1 at addresses h'020000 to h'03ffff h8s/2311, h8s/2313, and h8s/2316: reserved area * 1 addresses h'010000 to h'03ffff * 2 : expanded mode: external addresses single-chip mode: reserved area * 1 external address enable reserved (only 0 should be written to this bit.) (only 1 should be written to these bit.) wait pin enable 0 1 wait input by wait pin disabled wait input by wait pin enabled notes: 1. do not access a reserved area. 2. h'010000 to h'05ffff in the h8s/2315, and h'010000 to h'07ffff in the h8s/2319. reserved
346 ramer?am emulation register h'fedb flash memory (valid only in f-ztat version) 7 0 6 0 5 0 4 0 3 rams 0 r/w 0 ram0 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w bit initial value read/write : : : ram2 * 0 1 rams 0 1 ram select, flash memory area select ram1 * 0 1 0 1 ram0 * 0 1 0 1 0 1 0 1 ram area block name * : don't care h'ffdc00 to h'ffebff h'000000 to h'000fff h'001000 to h'001fff h'002000 to h'002fff h'003000 to h'003fff h'004000 to h'004fff h'005000 to h'005fff h'006000 to h'006fff h'007000 to h'007fff ram area, 4 kbytes eb0 (4 kbytes) eb1 (4 kbytes) eb2 (4 kbytes) eb3 (4 kbytes) eb4 (4 kbytes) eb5 (4 kbytes) eb6 (4 kbytes) eb7 (4 kbytes)
347 iscrh irq sense control register h h'ff2c interrupt controller iscrl irq sense control register l h'ff2d interrupt controller 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value read/write : : : iscrh 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w irq7 to irq4 sense control a, b irq3 to irq0 sense control a, b 0 1 0 1 0 1 irqn input low level falling edge of irqn input rising edge of irqn input both falling and rising edges of irqn input irqnscb irqnsca interrupt request generation (n = 7 to 0) bit initial value read/write : : : iscrl
348 ier?rq enable register h'ff2e interrupt controller 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w irqn enable 0 1 irqn interrupt disabled irqn interrupt enabled (n = 7 to 0) bit initial value read/write : : :
349 isr?rq status register h'ff2f interrupt controller 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value read/write : : : indicate the status of irq7 to irq0 interrupt requests bit n irqnf description 0 [clearing conditions] (initial value) ? when 0 is written to irqnf after reading irqnf = 1 ? when interrupt exception handling is executed while low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed while falling, rising, or both- edge detection is set (irqnscb = 1 or irqnsca = 1) ? when the dtc is activated by an irqn interrupt and the disel bit in the dtc's mrb register is 0 1 [setting conditions] ? when irqn input goes low while low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input while falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input while rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input while both-edge detection is set (irqnscb = irqnsca = 1) (n = 7 to 0) note: * can only be written with 0 for flag clearing.
350 dtcera to dtcerf?tc enable registers h'ff30 to h'ff34 dtc 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w dtc activation enable bit initial value read/write : : : dtc activation by this interrupt is disabled [clearing conditions] when the disel bit is 1 and data transfer has ended when the specified number of transfers have ended 0 1 dtc activation by this interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended correspondence between interrupt sources and dtcer bits register 76543210 dtcera irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 dtcerb adi tgi0a tgi0b tgi0c tgi0d tgi1a tgi1b dtcerc tgi2a tgi2b tgi3a tgi3b tgi3c tgi3d tgi4a tgi4b dtcerd tgi5a tgi5b cmia0 cmib0 cmia1 cmib1 dtcere rxi0 txi0 rxi1 txi1 note: for dtce bit setting, read/write operations must be performed using bit-manipulation instructions such as bset and bclr. for the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register.
351 dtvecr?tc vector register h'ff37 dtc 7 swdte 0 r/w 6 dtvec6 0 r/(w) * 5 dtvec5 0 r/(w) * 4 dtvec4 0 r/(w) * 3 dtvec3 0 r/(w) * 0 dtvec0 0 r/(w) * 2 dtvec2 0 r/(w) * 1 dtvec1 0 r/(w) * dtc software activation enable 0 1 dtc software activation is enabled [holding conditions] when the disel bit is 1 and data transfer has ended when the specified number of transfers have ended during data transfer due to software activation sets vector number for dtc software activation bit initial value read/write : : : note: * bits dtvec6 to dtvec0 can be written to when swdte = 0. dtc software activation is disabled [clearing conditions] when the disel bit is 0 and the specified number of transfers have not ended when 0 is written to the swdte bit after a software activated data transfer end interrupt (swdtend) has been requested of the cpu
352 sbycr?tandby control register h'ff38 power-down state 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 irq37s 0 r/w 2 0 1 0 software standby note: * cannot be used in the f-ztat version. 0 1 transition to sleep mode after execution of sleep instruction transition to software standby mode after execution of sleep instruction standby timer select 0 1 0 1 0 1 0 1 0 1 0 1 0 1 standby time = 8192 states standby time = 16384 states standby time = 32768 states standby time = 65536 states standby time = 131072 states standby time = 262144 states reserved standby time = 16 states * output port enable bit initial value read/write : : : irq37 software standby clear select 0 1 irq3 to irq7 cannot be used as software standby mode clearing sources irq3 to irq7 can be used as software standby mode clearing sources 0 1 in software standby mode, address bus and bus control signals are high-impedance in software standby mode, address bus and bus control signals retain output state
353 syscr?ystem control register h'ff39 mcu 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 lwrod 0 r/w 1 0 r/w bit initial value read/write : : : reserved only 0 should be written to this bit ram enable 0 on-chip ram disabled 1 on-chip ram enabled nmi input edge select 0 falling edge 1 rising edge interrupt control mode selection 0 1 interrupt control mode 0 0 1 0 1 setting prohibited interrupt control mode 2 setting prohibited lwr output disable 0 pf3 is designated as lwr output pin 1 pf3 is designated as i/o port, and does not function as lwr output pin reserved only 0 should be written to this bit
354 sckcr?ystem clock control register h'ff3a clock pulse generator 7 pstop 0 r/w 6 0 r/w 5 div 0 r/w 4 0 3 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w 0 1 pstop normal operation output fixed high high impedance high impedance fixed high fixed high clock output control system clock select division ratio select reserved only 0 should be written to this bit 0 1 0 1 0 1 0 1 0 1 0 1 bus master is in high-speed mode medium-speed clock is /2 medium-speed clock is /4 medium-speed clock is /8 medium-speed clock is /16 medium-speed clock is /32 bus master is in high-speed mode clock supplied to entire chip is /2 clock supplied to entire chip is /4 clock supplied to entire chip is /8 output fixed high sleep mode bit initial value read/write : : : software standby mode hardware standby mode div = 0 div = 1
355 mdcr?ode control register h'ff3b mcu 7 1 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r current mode pin operating mode bit initial value read/write : : : note: * determined by pins md2 to md0 mstpcrh module stop control register h h'ff3c power-down state mstpcrl module stop control register l h'ff3d power-down state 15 0 r/w 14 0 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w mstpcrh mstpcrl specifies module stop mode mstp bits and on-chip supporting modules 0 1 module stop mode cleared module stop mode set register mstpcrh mstpcrl bits mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 module dtc tpu 8-bit timer d/a a/d sci1 sci0 bit initial value read/write : : :
356 syscr2?ystem control register 2 h'ff42 flash memory (valid only in f-ztat version)) 7 0 6 0 5 0 4 0 3 flshe 0 r/w 0 0 2 0 1 0 bit initial value read/write : : : 0 1 flash memory control register enable flash memory control register is not selected for area h'ffffc8 to h'ffffcb flash memory control register is selected for area h'ffffc8 to h'ffffcb reserved register h'ff44 7 0 6 0 5 0 r/w 4 0 3 0 0 0 2 0 1 0 reserved only 0 should be written to these bits bit initial value read/write : : :
357 pfcr1?ort function control register 1 h'ff45 7 css17 0 r/w 6 css36 0 r/w 5 pf1cc5s 0 r/w 4 pf0cs45 0 r/w 3 a23e 1 r/w 0 a20e 1 r/w 2 a22e 1 r/w 1 a21e 1 r/w bit initial value read/write : : : 0 1 p10dr is output when p10ddr = 1 a20 is output when p10ddr = 1 address 20 output enable * 1 0 1 p11dr is output when p11ddr = 1 a21 is output when p11ddr = 1 address 21 output enable * 1 0 1 p12dr is output when p12ddr = 1 a22 is output when p12ddr = 1 address 22 output enable * 1 0 1 pf0 is pf0/ breq / irq0 pin pf0 is pf0/ breq / irq0 / cs4 pin. cs4 output is enabled when brle = 0, cs25e = 1, and pf0ddr = 1 port f0 chip select 4 select * 1 0 1 pf1 is pf1/ back / irq1 pin pf1 is pf1/ back / irq1 / cs5 pin. cs5 output is enabled when brle = 0, cs25e = 1, and pf1ddr = 1 port f1 chip select 5 select * 1 0 1 pg1 is pg1/ irq7 / cs3 pin. cs3 output is enabled when when cs25e = 1 and pg1ddr = 1 pg1 is pg1/ irq7 / cs6 pin. cs6 output is enabled when cs167e = 1 and pg1ddr = 1 cs36 select * 1, * 3 0 1 pg3 is pg3/ cs1 pin. cs1 output is enabled when cs167e = 1 and pg3ddr = 1 pg3 is pg3/ cs7 pin. cs7 output is enabled when cs167e = 1 and pg3ddr = 1 cs17 select * 1, * 2 notes: 1. valid in modes 4 to 6. 2. clear pg3ddr to 0 before changing the css17 bit setting. 3. clear pg1ddr to 0 before changing the css36 bit setting. 0 1 p13dr is output when p13ddr = 1 a23 is output when p13ddr = 1 address 23 output enable * 1
358 port1?ort 1 register h'ff50 port 1 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 0 p10 * r 2 p12 * r 1 p11 * r note: * determined by the state of pins p17 to p10. state of port 1 pins bit initial value read/write : : : port2?ort 2 register h'ff51 port 2 7 p27 * r 6 p26 * r 5 p25 * r 4 p24 * r 3 p23 * r 0 p20 * r 2 p22 * r 1 p21 * r state of port 2 pins note: * determined by the state of pins p27 to p20. bit initial value read/write : : : port3?ort 3 register h'ff52 port 3 7 undefined 6 undefined 5 p35 * r 4 p34 * r 3 p33 * r 0 p30 * r 2 p32 * r 1 p31 * r state of port 3 pins note: * determined by the state of pins p35 to p30. bit initial value read/write : : :
359 port4?ort 4 register h'ff53 port 4 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 0 p40 * r 2 p42 * r 1 p41 * r state of port 4 pins note: * determined by the state of pins p47 to p40. bit initial value read/write : : : porta?ort a register h'ff59 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3 * r 0 pa0 * r 2 pa2 * r 1 pa1 * r state of port a pins note: * determined by the state of pins pa3 to pa0. bit initial value read/write : : : portb?ort b register h'ff5a port b 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 0 pb0 * r 2 pb2 * r 1 pb1 * r state of port b pins note: * determined by the state of pins pb7 to pb0. bit initial value read/write : : :
360 portc?ort c register h'ff5b port c 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 0 pc0 * r 2 pc2 * r 1 pc1 * r state of port c pins note: * determined by the state of pins pc7 to pc0. bit initial value read/write : : : portd?ort d register h'ff5c port d 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 0 pd0 * r 2 pd2 * r 1 pd1 * r state of port d pins note: * determined by the state of pins pd7 to pd0. bit initial value read/write : : : porte?ort e register h'ff5d port e 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 0 pe0 * r 2 pe2 * r 1 pe1 * r state of port e pins note: * determined by the state of pins pe7 to pe0. bit initial value read/write : : :
361 portf?ort f register h'ff5e port f 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 0 pf0 * r 2 pf2 * r 1 pf1 * r state of port f pins note: * determined by the state of pins pf7 to pf0. bit initial value read/write : : : portg?ort g register h'ff5f port g 7 undefined 6 undefined 5 undefined 4 pg4 * r 3 pg3 * r 0 pg0 * r 2 pg2 * r 1 pg1 * r state of port g pins note: * determined by the state of pins pg4 to pg0. bit initial value read/write : : : p1dr?ort 1 data register h'ff60 port 1 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w stores output data for port 1 pins (p17 to p10) bit initial value read/write : : : p2dr?ort 2 data register h'ff61 port 2 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 0 p20dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w stores output data for port 2 pins (p27 to p20) bit initial value read/write : : :
362 p3dr?ort 3 data register h'ff62 port 3 7 undefined 6 undefined 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w stores output data for port 3 pins (p35 to p30) bit initial value read/write : : : padr?ort a data register h'ff69 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w stores output data for port a pins (pa3 to pa0) bit initial value read/write : : : pbdr?ort b data register h'ff6a port b 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w stores output data for port b pins (pb7 to pb0) bit initial value read/write : : : pcdr?ort c data register h'ff6b port c 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w stores output data for port c pins (pc7 to pc0) bit initial value read/write : : :
363 pddr?ort d data register h'ff6c port d 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w stores output data for port d pins (pd7 to pd0) bit initial value read/write : : : pedr?ort e data register h'ff6d port e 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w stores output data for port e pins (pe7 to pe0) bit initial value read/write : : : pfdr?ort f data register h'ff6e port f 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w stores output data for port f pins (pf7 to pf0) bit initial value read/write : : :
364 pgdr?ort g data register h'ff6f port g 7 undefined 6 undefined 5 undefined 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w stores output data for port g pins (pg4 to pg0) bit initial value read/write : : : papcr?ort a mos pull-up control register h'ff70 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w controls the mos input pull-up function incorporated into port a on a bit-by-bit basis bit initial value read/write : : : pbpcr?ort b mos pull-up control register h'ff71 port b 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w controls the mos input pull-up function incorporated into port b on a bit-by-bit basis bit initial value read/write : : :
365 pcpcr?ort c mos pull-up control register h'ff72 port c 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w controls the mos input pull-up function incorporated into port c on a bit-by-bit basis bit initial value read/write : : : pdpcr?ort d mos pull-up control register h'ff73 port d 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w controls the mos input pull-up function incorporated into port d on a bit-by-bit basis bit initial value read/write : : : pepcr?ort e mos pull-up control register h'ff74 port e 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w controls the mos input pull-up function incorporated into port e on a bit-by-bit basis bit initial value read/write : : :
366 p3odr?ort 3 open drain control register h'ff76 port 3 7 undefined 6 undefined 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w controls the pmos on/off status for each port 3 pin (p35 to p30) bit initial value read/write : : : paodr?ort a open drain control register h'ff77 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w controls the pmos on/off status for each port a pin (pa3 to pa0) bit initial value read/write : : :
367 smr0?erial mode register 0 h'ff78 sci0 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 0 1 parity bit addition and checking disabled parity bit addition and checking enabled * parity enable 0 1 even parity * 1 odd parity * 2 parity mode 0 1 multiprocessor function disabled multiprocessor format selected 1. when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. when odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. multiprocessor mode 0 1 1 stop bit 2 stop bits stop bit length notes: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. notes: 0 1 0 1 0 1 clock /4 clock /16 clock /64 clock clock select 0 1 8-bit data 7-bit data * character length bit initial value read/write : : : note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. with 7-bit data, it is not possible to select lsb-first or msb-first transfer.
368 smr0?erial mode register 0 h'ff78 smart card interface 0 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w 0 1 normal smart card interface mode operation tend flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generated 11.0 etu after beginning of start bit fixed high/low-level control possible (set in scr) in addition to clock output on/off control gsm mode 0 1 setting prohibited parity bit addition and checking enabled parity enable (set to 1 when using the smart card interface) 0 1 even parity * 1 odd parity * 2 parity mode 0 1 0 1 0 1 clock /4 clock /16 clock /64 clock clock select bit initial value read/write : : : note: etu (elementary time unit): interval for transfer of one bit 0 1 0 1 0 1 32 clocks 64 clocks 372 clocks 256 clocks base clock pulse bcp1 bcp0 base clock pulse 0 1 normal smart card interface mode block transfer mode block transfer mode select 1. when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. when odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. notes:
369 brr0?it rate register 0 h'ff79 sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w sets the serial transfer bit rate note: for details, see section 11.2.8, bit rate register (brr), in the hardware manual. bit initial value read/write : : :
370 scr0?erial control register 0 h'ff7a sci0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 1 0 asynchronous mode internal clock/sck pin functions as i/o port clock enable 0 1 transmit-end interrupt (tei) request disabled * 3 transmit-end interrupt (tei) request enabled * 3 transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupt enable 0 1 reception disabled * 5 reception enabled * 6 receive enable 0 1 transmission disabled * 7 transmission enabled * 8 transmit enable 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * 9 receive interrupt enable 0 1 transmit-data-empty interrupt (txi) request disabled * 10 transmit-data-empty interrupt (txi) request enabled transmit interrupt enable bit initial value read/write : : : synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input multiprocessor interrupts enabled * 4 receive-data-full interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled 1 0 1 0
371 notes: 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate. 3. tei clearing can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or by clearing the teie bit to 0. 4. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. 5. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 6. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr setting must be performed to decide the receive format before setting the re bit to 1. 7. the tdre flag in ssr is fixed at 1. 8. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transmit format before setting the te bit to 1. 9. rxi and eri interrupt requests can be cleared by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or by clearing the rie bit to 0. 10. txi interrupt requests can be cleared by reading 1 from the tdre flag, then clearing it to 0, or by clearing the tie bit to 0.
372 scr0?erial control register 0 h'ff7a smart card interface 0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w smcr smif 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 smr c/ a ,gm cke1 cke0 see sci specification sck pin function clock enable (when bit 7 of smr is set to 1 in smart card interface mode) scr setting 0 1 transmit-end interrupt (tei) request disabled * 1 transmit-end interrupt (tei) request enabled * 1 transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when data with mpb = 1 is received multiprocessor interrupt enable 0 1 reception disabled * 3 reception enabled * 4 receive enable 0 1 transmission disabled * 5 transmission enabled * 6 transmit enable 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * 7 receive interrupt enable 0 1 transmit-data-empty interrupt (txi) request disabled * 8 transmit-data-empty interrupt (txi) request enabled transmit interrupt enable bit initial value read/write : : : multiprocessor interrupts enabled * 2 receive-data-full interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled operates as port i/o pin clock output as sck output pin fixed-low output as sck output pin clock output as sck output pin fixed-high output as sck output pin clock output as sck output pin
373 notes: 1. tei clearing can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or by clearing the teie bit to 0. 2. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. 3. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 4. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr setting must be performed to decide the receive format before setting the re bit to 1. 5. the tdre flag in ssr is fixed at 1. 6. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transmit format before setting the te bit to 1. 7. rxi and eri interrupt requests can be cleared by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or by clearing the rie bit to 0. 8. txi interrupt requests can be cleared by reading 1 from the tdre flag, then clearing it to 0, or by clearing the tie bit to 0. tdr0?ransmit data register 0 h'ff7b sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w stores data for serial transmission bit initial value read/write : : :
374 ssr0?erial status register 0 h'ff7c sci0 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr 7 tdre 1 r/(w) * 1 6 rdrf 0 r/(w) * 1 5 orer 0 r/(w) * 1 4 fer 0 r/(w) * 1 3 per 0 r/(w) * 1 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r 0 transmit data register empty 0 receive data register full * 9 0 overrun error 0 framing error 0 parity error 0 transmit end [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received * 2 [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing condition] when 0 is written to per after reading per = 1 * 3 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr * 4 [clearing condition] when 0 is written to fer after reading fer = 1 * 5 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 6 [clearing condition] when 0 is written to orer after reading orer = 1 * 7 [setting condition] when the next serial reception is completed while rdrf = 1 * 8 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr 1 1 1 1 1 1 1
375 notes: 1. can only be written with 0 for flag clearing. 2. retains its previous state when the re bit in scr is cleared to 0 with a multiprocessor format. 3. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission is also disabled. 5. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 6. in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. serial reception cannot be continued while the fer flag is set to 1. in synchronous mode, serial transmission is also disabled. 7. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 8. the receive data prior to the overrun error is retained in rdr, and data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission is also disabled. 9. rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
376 ssr0?erial status register 0 h'ff7c smart card interface 0 7 tdre 1 r/(w) * 1 6 rdrf 0 r/(w) * 1 5 orer 0 r/(w) * 1 4 ers 0 r/(w) * 1 3 per 0 r/(w) * 1 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r 0 transmit data register empty 0 receive data register full * 9 0 overrun error 0 error signal status * 6 0 parity error 0 transmit end transmission in progress [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received * 2 [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : transmission has ended [setting conditions] on reset, or in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu * 3 after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 [clearing condition] when 0 is written to per after reading per = 1 * 4 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr * 5 data has been received normally, and there is no error signal [clearing conditions] on reset, or in standby mode or module stop mode when 0 is written to ers after reading ers = 1 error signal indicating detection of parity error has been sent by receiving device [setting condition] when the error signal is sampled at the low level [clearing condition] when 0 is written to orer after reading orer = 1 * 7 [setting condition] when the next serial reception is completed while rdrf = 1 * 8 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr 1 1 1 1 1 1 1
377 notes: 1. can only be written with 0 for flag clearing. 2. retains its previous state when the re bit in scr is cleared to 0 with a multiprocessor format. 3. etu (elementary time unit): interval for transfer of one bit 4. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 5. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission is also disabled. 6. clearing the te bit in scr to 0 does not affect the ers flag, which retains its prior state. 7. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 8. the receive data prior to the overrun error is retained in rdr, and data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission is also disabled. 9. rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
378 rdr0?eceive data register 0 h'ff7d sci0, smart card interface 0 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write : : : stores received serial data scmr0?mart card mode register 0 h'ff7e sci0, smart card interface 0 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 0 1 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first smart card data direction 0 1 tdr contents are transmitted as they are receive data is stored in rdr as it is smart card data invert 0 1 smart card interface function is disabled smart card interface mode select bit initial value read/write : : : smart card interface function is enabled tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form tdr contents are transmitted msb-first receive data is stored in rdr msb-first
379 smr1?erial mode register 1 h'ff80 sci1 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 1 asynchronous mode synchronous mode asynchronous mode/synchronous mode select 0 1 parity bit addition and checking disabled parity bit addition and checking enabled * parity enable 0 1 even parity * 1 odd parity * 2 parity mode 0 1 1 stop bit 2 stop bits stop bit length 0 1 multiprocessor function disabled multiprocessor format selected multiprocessor mode 0 1 0 1 0 1 clock /4 clock /16 clock /64 clock clock select bit initial value read/write : : : 0 1 8-bit data 7-bit data * character length note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. with 7-bit data, it is not possible to select lsb-first or msb-first transfer. 1. when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. when odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. notes: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. notes:
380 smr1?erial mode register 1 h'ff80 smart card interface 1 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w 0 1 normal smart card interface mode operation tend flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generated 11.0 etu after beginning of start bit fixed high/low-level control possible (set in scr) in addition to clock output on/off control gsm mode 0 1 setting prohibited parity bit addition and checking enabled * parity enable 0 1 even parity * 1 odd parity * 2 parity mode (set to 1 when using the smart card interface) 0 1 0 1 0 1 clock /4 clock /16 clock /64 clock clock select bit initial value read/write : : : note: etu (elementary time unit): interval for transfer of one bit 0 1 0 1 0 1 32 clocks 64 clocks 372 clocks 256 clocks base clock pulse bcp1 bcp0 base clock pulse 0 1 normal smart card interface mode block transfer mode block transfer mode select 1. when even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. when odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. notes: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. notes:
381 brr1?it rate register 1 h'ff81 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: for details, see section 11.2.8, bit rate register (brr), in the hardware manual. sets the serial transfer bit rate bit initial value read/write : : :
382 scr1?erial control register 1 h'ff82 sci1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 1 0 asynchronous mode internal clock/sck pin functions as i/o port clock enable 0 1 transmit-end interrupt (tei) request disabled * 3 transmit-end interrupt (tei) request enabled * 3 transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupt enable 0 1 reception disabled * 5 reception enabled * 6 receive enable 0 1 transmission disabled * 7 transmission enabled * 8 transmit enable 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * 9 receive interrupt enable 0 1 transmit-data-empty interrupt (txi) request disabled transmit-data-empty interrupt (txi) request enabled * 10 transmit interrupt enable bit initial value read/write : : : synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 synchronous mode external clock/sck pin functions as serial clock input multiprocessor interrupts enabled * 4 receive-data-full interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled 1 0 1 0
383 notes: 1. outputs a clock of the same frequency as the bit rate. 2. inputs a clock with a frequency 16 times the bit rate. 3. tei clearing can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or by clearing the teie bit to 0. 4. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. 5. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 6. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr setting must be performed to decide the receive format before setting the re bit to 1. 7. the tdre flag in ssr is fixed at 1. 8. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transmit format before setting the te bit to 1. 9. rxi and eri interrupt requests can be cleared by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or by clearing the rie bit to 0. 10. txi interrupt requests can be cleared by reading 1 from the tdre flag, then clearing it to 0, or by clearing the tie bit to 0.
384 scr1?erial control register 1 h'ff82 smart card interface 1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w scmr smif 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 smr c/ a ,gm cke1 cke0 see sci specification sck pin function clock enable (when bit 7 of smr is set to 1 in smart card interface mode) scr setting 0 1 transmit-end interrupt (tei) request disabled * 1 transmit-end interrupt (tei) request enabled * 1 transmit end interrupt enable 0 multiprocessor interrupts disabled [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupt enable 0 1 reception disabled * 3 reception enabled * 4 receive enable 0 1 transmission disabled * 5 transmission enabled * 6 transmit enable 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * 7 receive interrupt enable 0 1 transmit-data-empty interrupt (txi) request disabled * 8 transmit-data-empty interrupt (txi) request enabled transmit interrupt enable bit initial value read/write : : : multiprocessor interrupts enabled * 2 receive-data-full interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received 1 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled operates as port i/o pin clock output as sck output pin fixed-low output as sck output pin clock output as sck output pin fixed-high output as sck output pin clock output as sck output pin
385 notes: 1. tei clearing can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or by clearing the teie bit to 0. 2. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. 3. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 4. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr setting must be performed to decide the receive format before setting the re bit to 1. 5. the tdre flag in ssr is fixed at 1. 6. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transmit format before setting the te bit to 1. 7. rxi and eri interrupt requests can be cleared by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or by clearing the rie bit to 0. 8. txi interrupt requests can be cleared by reading 1 from the tdre flag, then clearing it to 0, or by clearing the tie bit to 0. tdr1?ransmit data register 1 h'ff83 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w stores data for serial transmission bit initial value read/write : : :
386 ssr1?erial status register 1 h'ff84 sci1 7 tdre 1 r/(w) * 1 6 rdrf 0 r/(w) * 1 5 orer 0 r/(w) * 1 4 fer 0 r/(w) * 1 3 per 0 r/(w) * 1 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r 0 transmit data register empty 0 receive data register full * 9 0 overrun error 0 framing error 0 parity error 0 transmit end 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received * 2 multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting condition] when data with a 1 multiprocessor bit is received [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character 1 [clearing condition] when 0 is written to per after reading per = 1 * 3 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 4 1 [clearing condition] when 0 is written to fer after reading fer = 1 * 5 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 6 [clearing condition] when 0 is written to orer after reading orer = 1 * 7 [setting condition] when the next serial reception is completed while rdrf = 1 * 8 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr 1 1 1 1 1
387 notes: 1. can only be written with 0 for flag clearing. 2. retains its previous state when the re bit in scr is cleared to 0 with a multiprocessor format. 3. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 4. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission is also disabled. 5. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 6. in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. serial reception cannot be continued while the fer flag is set to 1. in synchronous mode, serial transmission is also disabled. 7. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 8. the receive data prior to the overrun error is retained in rdr, and data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission is also disabled. 9. rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
388 ssr1?erial status register 1 h'ff84 smart card interface 1 7 tdre 1 r/(w) * 1 6 rdrf 0 r/(w) * 1 5 orer 0 r/(w) * 1 4 ers 0 r/(w) * 1 3 per 0 r/(w) * 1 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r transmit data register empty 0 receive data register full * 9 0 overrun error 0 error signal status * 6 0 parity error 0 transmit end 0 multiprocessor bit [clearing condition] when data with a 0 multiprocessor bit is received * 2 multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted bit initial value read/write : : : [setting condition] when data with a 1 multiprocessor bit is received transmission in progress [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr transmission has ended [setting conditions] on reset, or in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu * 3 after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 1 [clearing condition] when 0 is written to per after reading per = 1 * 4 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 5 1 data has been received normally, and there is no error signal [clearing conditions] on reset, or in standby mode or module stop mode when 0 is written to ers after reading ers =1 error signal indicating detection of parity error has been sent by receiving device [setting condition] when the error signal is sampled at the low level [clearing condition] when 0 is written to orer after reading orer = 1 * 7 [setting condition] when the next serial reception is completed while rdrf = 1 * 8 [clearing conditions] when 0 is written to rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr 1 1 1 1 0 1
389 notes: 1. can only be written with 0 for flag clearing. 2. retains its previous state when the re bit in scr is cleared to 0 with a multiprocessor format. 3. etu (elementary time unit): interval for transfer of one bit 4. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 5. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission is also disabled. 6. clearing the te bit in scr to 0 does not affect the ers flag, which retains its prior state. 7. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 8. the receive data prior to the overrun error is retained in rdr, and data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission is also disabled. 9. rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost.
390 rdr1?eceive data register 1 h'ff85 sci1, smart card interface 1 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r stores received serial data bit initial value read/write : : : scmr1?mart card mode register 1 h'ff86 sci1, smart card interface 1 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 0 1 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first smart card data direction 0 tdr contents are transmitted as they are receive data is stored in rdr as it is smart card data invert 0 1 smart card interface function is disabled smart card interface mode select bit initial value read/write : : : smart card interface function is enabled tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
391 addrah a/d data register ah h'ff90 a/d converter addral a/d data register al h'ff91 a/d converter addrbh a/d data register bh h'ff92 a/d converter addrbl a/d data register bl h'ff93 a/d converter addrch a/d data register ch h'ff94 a/d converter addrcl a/d data register cl h'ff95 a/d converter addrdh a/d data register dh h'ff96 a/d converter addrdl a/d data register dl h'ff97 a/d converter 15 ad9 0 r 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r stores the results of a/d conversion analog input channel a/d data register bit initial value read/write : : : addra addrb addrc addrd group 0 an0 an1 an2 an3 group 1 an4 an5 an6 an7
392 adcsr?/d control/status register h'ff98 a/d converter [clearing conditions] when 0 is written to the adf flag after reading adf = 1 when the dtc is activated by an adi interrupt, and addr is read 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w note: * can only be written with 0 for flag clearing. 0 1 a/d conversion end interrupt request disabled a/d conversion end interrupt request enabled a/d interrupt enable 0 1 single mode scan mode scan mode group selection ch2 ch1 ch0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 an0 (initial value) an1 an2 an3 an4 an5 an6 an7 an0 an0, an1 an0 to an2 an0 to an3 an4 an4, an5 an4 to an6 an4 to an7 channel selection description 0 1 a/d conversion stopped a/d start 0 a/d end flag bit initial value read/write : : : single mode: a/d conversion is started. cleared to 0 automatically when conversion ends scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or transition to standby mode or module stop mode [setting conditions] single mode: when a/d conversion ends scan mode: when a/d conversion ends on all specified channels 1 0 1 0 1 0 1 description clock select conversion time = 530 states (max.) conversion time = 68 states (max.) conversion time = 266 states (max.) (initial value) conversion time = 134 states (max.) cks cks1 bit 3 adcr bit 3 single mode (scan = 0) scan mode (scan = 1) channel select note: these bits select the analog input channel(s). ensure that conversion is halted (adst = 0) before making a channel setting.
393 adcr?/d control register h'ff99 a/d converter 7 trgs1 0 r/w 6 trgs0 0 r/w 5 1 4 1 3 cks1 1 r/w 0 1 2 1 r/w 1 1 0 1 0 1 0 1 description timer trigger select bit initial value read/write : : : a/d conversion start by external trigger is disabled a/d conversion start by external trigger (tpu) is enabled a/d conversion start by external trigger (8-bit timer) is enabled a/d conversion start by external trigger pin ( adtrg ) is enabled trgs1 trgs1 0 1 0 1 0 1 description clock select reserved (only 1 should be written to this bit.) conversion time = 530 states (max.) conversion time = 68 states (max.) conversion time = 266 states (max.) (initial value) conversion time = 134 states (max.) cks cks1 adcsr bit 3 bit 3 dadr0?/a data register 0 h'ffa4 d/a converter dadr1?/a data register 1 h'ffa5 d/a converter 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w stores data for d/a conversion bit initial value read/write : : :
394 dacr01?/a control register 01 h'ffa6 d/a converter 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 d/a conversion control daoe1 daoe0 dae description 0 1 0 1 0 1 * 0 1 0 1 * channel 0 and 1 d/a conversion disabled channel 0 d/a conversion enabled channel 1 d/a conversion disabled channel 0 and 1 d/a conversion enabled channel 0 d/a conversion disabled channel 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled * : don't care 0 1 analog output da0 is disabled channel 0 d/a conversion is enabled d/a output enable 0 0 1 analog output da1 is disabled channel 1 d/a conversion is enabled d/a output enable 1 bit initial value read/write : : : analog output da0 is enabled analog output da1 is enabled
395 pfcr2?ort function control register 2 h'ffac ports 0 1 pf6 is designated as as output pin pf6 is designated as i/o port, and does not function as as output pin as output disable * 1 0 1 cs2 , cs3 , cs4 , and cs5 output disabled (can be used as i/o ports) cs2 , cs3 , cs4 , and cs5 output enabled cs25 enable * 1, * 2 0 1 cs1 , cs6 , and cs7 output disabled (can be used as i/o ports) cs1 , cs6 , and cs7 output enabled cs167 enable * 1, * 3 reserved only 0 should be written to these bits 7 0 r/w 6 0 r/w 5 cs167e 1 r/w 4 cs25e 1 r/w 3 asod 0 r/w 0 0 r 2 0 r 1 0 r bit initial value read/write : : : notes: 1. this bit is valid in modes 4 to 6. 2. clear the ddr bits to 0 before changing the cs25e setting. 3. clear the ddr bits to 0 before changing the cs167e setting.
396 tcr0?ime control register 0 h'ffb0 8-bit timer channel 0 tcr1?ime control register 1 h'ffb1 8-bit timer channel 1 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w note: * 000 1 clock input disabled internal clock: counted at falling edge of /8 internal clock: counted at falling edge of /64 10 internal clock: counted at falling edge of /8192 1 1 0 0 for channel 0: count at tcnt1 overflow signal * for channel 1: count at tcnt0 compare match a * external clock: counted at rising edge external clock: counted at falling edge 1 0 1 external clock: counted at both rising and falling edges 1 clock select 0 1 cmfb interrupt requests (cmib) are disabled cmfb interrupt requests (cmib) are enabled compare match interrupt enable b 0 1 cmfa interrupt requests (cmia) are disabled cmfa interrupt requests (cmia) are enabled compare match interrupt enable a 0 1 ovf interrupt requests (ovi) are disabled ovf interrupt requests (ovi) are enabled timer overflow interrupt enable 0 1 clear is disabled clear by compare match a clear by compare match b clear by rising edge of external reset input 0 1 0 1 counter clear bit initial value read/write if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. : : :
397 tcsr0?imer control/status register 0 h'ffb2 8-bit timer channel 0 tcsr1?imer control/status register 1 h'ffb3 8-bit timer channel 1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w tcsr1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w tcsr0 note: * only 0 can be written to bits 7 to 5, to clear these flags. 0 1 compare match flag b 0 1 compare match flag a 0 [clearing condition] when 0 is written to ovf after reading ovf = 1 1 timer overflow flag 0 1 a/d converter start requests by compare match a are disabled a/d converter start requests by compare match a are enabled a/d trigger enable (tcsr0 only) 0 1 no change when compare match b occurs 0 is output when compare match b occurs 1 is output when compare match b occurs 0 1 0 1 output select bit initial value read/write : : : bit initial value read/write : : : [setting condition] when tcnt overflows (changes from h'ff to h'00) [clearing conditions] when 0 is written to cmfa after reading cmfa = 1 when the dtc is activated by a cmia interrupt, while the disel bit of mrb in dtc is 0 [setting condition] when tcnt matches tcora [clearing conditions] when 0 is written to cmfb after reading cmfb = 1 when the dtc is activated by a cmib interrupt, while the disel bit of mrb in dtc is 0 [setting condition] when tcnt matches tcorb output is inverted when compare match b occurs (toggle output) 0 no change when compare match a occurs 0 output select output is inverted when compare match a occurs (toggle output) 1 is output when compare match a occurs 0 is output when compare match a occurs 1 1 0 1
398 tcora0?ime constant register a0 h'ffb4 8-bit timer channel 0 tcora1?ime constant register a1 h'ffb5 8-bit timer channel 1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 bit initial value read/write : : : tcorb0?ime constant register b0 h'ffb6 8-bit timer channel 0 tcorb1?ime constant register b1 h'ffb7 8-bit timer channel 1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 bit initial value read/write : : : tcnt0?imer counter 0 h'ffb8 8-bit timer channel 0 tcnt1?imer counter 1 h'ffb9 8-bit timer channel 1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 bit initial value read/write : : :
399 tcsr?imer control/status register h'ffbc (w) h'ffbc (r) wdt notes: the method for writing to tcsr is different from that for general registers to prevent accidental overwriting. for details, see section 10.2.4, notes on register access, in the hardware manual. 1. can only be written with 0 for flag clearing. 2. the wdtovf pin function cannot be used in the f-ztat version. 0 [clearing condition] when 0 is written to ovf after reading ovf = 1 1 overflow flag 0 interval timer mode: sends the cpu an interval timer interrupt request (wovi) when tcnt overflows watchdog timer mode: generates the wdtovf signal * 2 when tcnt overflows 1 timer mode select 0 1 tcnt is initialized to h'00 and halted tcnt counts timer enable clock select cks2 cks1 cks0 clock overflow period * (when = 20 mhz) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 /2 (initial value) /64 /128 /512 /2048 /8192 /32768 /131072 25.6 s 819.2 s 1.6ms 6.6ms 26.2ms 104.9ms 419.4ms 1.68s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. [setting condition] when tcnt overflows from h'ff to h'00 in interval timer mode 7 ovf 0 r/(w) * 1 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write : : :
400 tcnt?imer counter h'ffbc (w) h'ffbd (r) wdt 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write : : : note: the method for writing to tcnt different from that for general registers to prevent accidental overwritting. for details, see section 10.2.4, notes on register access, in the hardware manual. rstcsr?eset control/status register h'ffbe (w) h'ffbf (r) wdt 7 wovf 0 r/(w) * 6 rste 0 r/w 5 0 r/w 4 1 3 1 0 1 2 1 1 1 0 1 [clearing condition] when 0 is written to wovf after reading wovf = 1 watchdog timer overflow flag notes: the method for writing to rstcsr is different from that for general registers to prevent accidental overwriting. for details, see section 10.2.4, notes on register access, in the hardware manual. * can only be written with 0 for flag clearing. 0 1 reset enable reset signal is not generated if tcnt overflows * reset signal is generated if tcnt overflows reserved this bit cannot be modified bit initial value read/write : : : [setting condition] when tcnt overflows (changes from h'ff to h'00) during watchdog timer operation note: * the modules in the chip are not reset, but tcnt and tcsr in wdt are reset.
401 tstr?imer start register h'ffc0 tpu 7 0 6 0 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w counter start 0 1 tcntn count operation is stopped tcntn performs count operation note: (n = 5 to 0) if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. bit initial value read/write : : : tsyr?imer synchro register h'ffc1 tpu 7 0 6 0 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w timer synchronization 0 1 tcntn operates independently (tcnt presetting/ clearing is unrelated to other channels) (n = 5 to 0) notes: to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. 1. 2. bit initial value read/write : : : tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible
402 flmcr1?lash memory control register 1 h'ffc8 flash memory (valid in h8s/2318 f-ztat and h8s/2315 f-ztat versions only) 7 fwe 1/0 * 1 r 6 swe 0 r/w 5 esu 0 r/w 4 psu 0 r/w 3 ev 0 r/w 0 p 0 r/w 2 pv 0 r/w 1 e 0 r/w bit initial value read/write : : : program * 2 0 program mode cleared 1 transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1 erase * 2 0 erase mode cleared 1 transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 program-verify * 2 0 program-verify mode cleared 1 transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 software write enable * 2 0 writes disabled 1 writes enabled [setting condition] when fwe = 1 flash write enable notes: 1. determined by the state of the fwe pin. 2. valid for addresses h'000000 to h'03ffff in h8s/2318 f-ztat and h'000000 to h'05ffff in h8s/2315 f-ztat. 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin erase-verify * 2 0 erase-verify mode cleared 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 program setup * 2 0 program setup cleared 1 program setup [setting condition] when fwe = 1 and swe = 1 erase setup * 2 0 erase setup cleared 1 erase setup [setting condition] when fwe = 1 and swe = 1
403 flmcr1?lash memory control register 1 h'ffc8 flash memory (valid in h8s/2319 f-ztat version only) 7 fwe 1 r 6 swe1 0 r/w 5 esu1 0 r/w 4 psu1 0 r/w 3 ev1 0 r/w 0 p1 0 r/w 2 pv1 0 r/w 1 e1 0 r/w bit initial value read/write : : : program 1 * 0 program mode cleared 1 transition to program mode [setting condition] when swe1 = 1 and psu1 = 1 erase 1 * 0 erase mode cleared 1 transition to erase mode [setting condition] when swe1 = 1 and esu1 = 1 program-verify 1 * 0 program-verify mode cleared 1 transition to program-verify mode [setting condition] when swe1 = 1 software write enable 1 * 0 writes disabled 1 writes enabled flash write enable always read as 1 and cannot be written to. note: * valid for addresses h'000000 to h'03ffff. erase-verify 1 * 0 erase-verify mode cleared 1 transition to erase-verify mode [setting condition] when swe1 = 1 program setup 1 * 0 program setup cleared 1 program setup [setting condition] when swe1 = 1 erase setup 1 * 0 erase setup cleared 1 erase setup [setting condition] when swe1 = 1
404 flmcr2?lash memory control register 2 h'ffc9 flash memory (valid in h8s/2318 f-ztat and h8s/2315 f-ztat versions only) 7 fler 0 r 6 0 5 0 4 0 3 0 0 0 2 0 1 0 bit initial value read/write : : : flash memory error 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 17.8.3, error protection, in the hardware manual.
405 flmcr2?lash memory control register 2 h'ffc9 flash memory (valid in h8s/2319 f-ztat version only) 7 fler 0 r 6 swe2 0 r/w 5 esu2 0 r/w 4 psu2 0 r/w 3 ev2 0 r/w 0 p2 0 r/w 2 pv2 0 r/w 1 e2 0 r/w bit initial value read/write : : : program 2 * 0 program mode cleared 1 transition to program mode [setting condition] when swe2 = 1 and psu2 = 1 erase 2 * 0 erase mode cleared 1 transition to erase mode [setting condition] when swe2 = 1 and esu2 = 1 program-verify 2 * 0 program-verify mode cleared 1 transition to program-verify mode [setting condition] when swe2 = 1 software write enable 2 * 0 writes disabled 1 writes enabled note: * valid for addresses h'040000 to h'07ffff. erase-verify 2 * 0 erase-verify mode cleared 1 transition to erase-verify mode [setting condition] when swe2 = 1 program setup 2 * 0 program setup cleared 1 program setup [setting condition] when swe2 = 1 erase setup 2 * 0 erase setup cleared 1 erase setup [setting condition] when swe2 = 1 flash memory error 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 17.8.3, error protection, in the hardware manual.
406 ebr1?rase block register 1 h'ffca flash memory ebr2?rase block register 2 h'ffcb flash memory (valid only in f-ztat version) 7 eb7 0 r/w 6 eb6 0 r/w 5 eb5 0 r/w 4 eb4 0 r/w 3 eb3 0 r/w 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w bit ebr1 initial value read/write : : : 7 eb15 * 2 0 r/w * 2 6 eb14 * 2 0 r/w * 2 5 eb13 * 1 0 r/w * 1 4 eb12 * 1 0 r/w * 1 3 eb11 0 r/w 0 eb8 0 r/w 2 eb10 0 r/w 1 eb9 0 r/w bit ebr2 initial value read/write notes: 1. valid in h8s/2319 f-ztat and h8s/2315 f-ztat versions. 2. valid in h8s/2319 f-ztat version. : : :
407 tcr0?imer control register 0 h'ffd0 tpu0 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel counter clear 0 0 1 0 1 0 1 0 1 clock edge 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input external clock: counts on tclkd pin input time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 bit initial value read/write : : : notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 10 1 0 1 0 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 note: the internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if /1 or overflow/underflow on another channel is selected as the input clock.
408 tmdr0?imer mode register 0 h'ffd1 tpu0 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w 0 1 tgrb buffer operation tgrb operates normally 0 1 tgra buffer operation tgra operates normally 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * notes: 1. 2. md3 is a reserved bit. in a write, it should always be written with 0. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. * : don't care bit initial value read/write : : : tgra and tgrc used together for buffer operation tgrb and tgrd used together for buffer operation
409 tior0h?imer i/o control register 0h h'ffd2 tpu0 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 1 tgr0b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr0a is output compare register tgr0a i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges * : don't care * : don't care note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000, and /1 is used as the tcnt1 count clock, this setting is invalid and input capture does not occur. bit initial value read/write : : : initial output is 0 output tgr0a is input capture register output disabled initial output is 1 output capture input source is tioca0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down tgr0b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr0b is input capture register output disabled initial output is 0 output capture input source is tiocb0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down * 1
410 tior0l?imer i/o control register 0l h'ffd3 tpu0 0 1 tgr0d i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 tgr0c i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * * : don't care * : don't care notes: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000, and /1 is used as the tcnt1 count clock, this setting is invalid and input capture does not occur. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare does not occur. note: when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare does not occur. 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer regis ter. bit initial value read/write : : : : tgr0c is output compare register * output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr0c is input capture register * output disabled initial output is 1 output capture input source is tiocc0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down tgr0d is output compare register * 2 output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr0d is input capture register * 2 output disabled initial output is 1 output capture input source is tiocd0 pin capture input source is channel 1/count clock input capture at tcnt1 count-up/ count-down * 1
411 tier0?imer interrupt enable register 0 h'ffd4 tpu0 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable tgr interrupt enable d tgr interrupt enable c tgr interrupt enable b 0 1 interrupt request (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 interrupt request (tgib) by tgfb bit disabled 0 1 interrupt request (tgic) by tgfc bit disabled 0 1 interrupt request (tgid) by tgfd bit disabled bit initial value read/write : : : interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit enabled interrupt request (tgic) by tgfc bit enabled interrupt request (tgid) by tgfd bit enabled
412 tsr0?imer status register 0 h'ffd5 tpu0 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * note: * can only be written with 0 for flag clearing. 0 overflow flag 1 0 input capture/output compare flag d 1 0 input capture/output compare flag c 1 0 input capture/output compare flag b 1 0 [clearing conditions] when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 bit initial value read/write : : : [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing conditions] when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing conditions] when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfc after reading tgfc = 1 [setting conditions] when tcnt = tgrc while tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register [clearing conditions] when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfd after reading tgfd = 1 [setting conditions] when tcnt = tgrd while tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 )
413 tcnt0?imer counter 0 h'ffd6 tpu0 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter tgr0a?imer general register 0a h'ffd8 tpu0 tgr0b?imer general register 0b h'ffda tpu0 tgr0c?imer general register 0c h'ffdc tpu0 tgr0d?imer general register 0d h'ffde tpu0 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write : : :
414 tcr1?imer control register 1 h'ffe0 tpu1 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 0 1 clock edge * 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input external clock: counts on tclkb pin input internal clock: counts on /256 counts on tcnt2 overflow/underflow time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: this setting is ignored when channel 1 is in phase counting mode. note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. bit initial value read/write : : : note: this setting is ignored when channel 1 is in phase counting mode. the internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if /1 or overflow/underflow on another channel is selected as the input clock. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *
415 tmdr1?imer mode register 1 h'ffe1 tpu1 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * note: md3 is a reserved bit. in a write, it should always be written with 0. * : don't care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : :
416 tior1?imer i/o control register 1 h'ffe2 tpu1 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 1 tgr1b i/o control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * tgr1a i/o control * : don't care 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * * : don't care bit initial value read/write : : : tgr1a is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr1a is input capture register output disabled initial output is 1 output capture input source is tioca1 pin capture input source is tgr0a compare match/ input capture input capture at generation of channel 0/tgr0a compare match/ input capture tgr1b is output compare register output disabled 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges initial output is 0 output tgr1b is input capture register output disabled initial output is 1 output capture input source is tiocb1 pin capture input source is tgr0c compare match/ input capture input capture at generation of tgr0c compare match/input capture
417 tier1?imer interrupt enable register 1 h'ffe4 tpu1 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled underflow interrupt enable tgr interrupt enable b 0 1 interrupt request (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 interrupt request (tgib) by tgfb bit disabled 0 1 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable bit initial value read/write : : : interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit enabled
418 tsr1?imer status register 1 h'ffe5 tpu1 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * 0 1 tcnt counts down tcnt counts up count direction flag 0 underflow flag 1 0 overflow flag 1 0 input capture/output compare flag b 1 0 [clearing conditions] when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 note: * can only be written with 0 for flag clearing. bit initial value read/write : : : [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing conditions] when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff)
419 tcnt1?imer counter 1 h'ffe6 tpu1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * up/down-counter * bit initial value read/write : : : this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. tgr1a?imer general register 1a h'ffe8 tpu1 tgr1b?imer general register 1b h'ffea tpu1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write : : :
420 tcr2?imer control register 2 h'fff0 tpu2 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture counter clear 0 1 0 1 0 1 0 1 clock edge * 0 1 count at rising edge count at falling edge count at both edges internal clock: counts on /1 internal clock: counts on /4 internal clock: counts on /16 internal clock: counts on /64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input internal clock: counts on /1024 time prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w note: this setting is ignored when channel 2 is in phase counting mode. note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. bit initial value read/write : : : note: this setting is ignored when channel 2 is in phase counting mode. the internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if /1 or overflow/underflow on another channel is selected as the input clock. tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *
421 tmdr2?imer mode register 2 h'fff1 tpu2 0 1 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * note: md3 is a reserved bit. in a write, it should always be written with 0. * : don't care 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value read/write : : :
422 tior2?imer i/o control register 2 h'fff2 tpu2 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w 0 1 tgr2b i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * : don't care 0 1 tgr2a is output compare register tgr2a i/o control 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges * : don't care bit initial value read/write : : : output disabled initial output is 0 output output disabled initial output is 1 output tgr2a is input capture register capture input source is tioca2 pin tgr2b is output compare register 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges output disabled initial output is 0 output output disabled initial output is 1 output tgr2b is input capture register capture input source is tiocb2 pin
423 tier2?imer interrupt enable register 2 h'fff4 tpu2 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled a/d conversion start request enable 0 1 interrupt request (tciu) by tcfu disabled interrupt request (tciu) by tcfu enabled underflow interrupt enable tgr interrupt enable b 0 1 interrupt request (tgia) by tgfa bit disabled tgr interrupt enable a 0 1 interrupt request (tgib) by tgfb bit disabled 0 1 interrupt request (tciv) by tcfv disabled interrupt request (tciv) by tcfv enabled overflow interrupt enable bit initial value read/write : : : interrupt request (tgia) by tgfa bit enabled interrupt request (tgib) by tgfb bit enabled
424 tsr2?imer status register 2 h'fff5 tpu2 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * 0 1 tcnt counts down tcnt counts up count direction flag 0 underflow flag 1 0 overflow flag 1 0 input capture/output compare flag b 1 0 [clearing conditions] when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 input capture/output compare flag a 1 note: * can only be written with 0 for flag clearing. bit initial value read/write : : : [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register [clearing conditions] when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff)
425 tcnt2?imer counter 2 h'fff6 tpu2 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * this timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. in other cases it functions as an up-counter. up/down-counter * bit initial value read/write : : : tgr2a?imer general register 2a h'fff8 tpu2 tgr2b?imer general register 2b h'fffa tpu2 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write : : :
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h8s/2319, h8s/2318 series, h8s/2319 f-ztat, h8s/2318 f-ztat, h8s/2315 f-ztat reference manual publication date: 1st edition, november 1999 2nd edition, august 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 1999. all rights reserved. printed in japan.

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